Analysis, Dimensioning and Robust Control of Shunt Active Filter for Harmonic Currents Compensation in Electrical Mains

In this chapter some results related to Shunt Active Filters (SAFs) and obtained by the authors and some coauthors are reported. SAFs are complex power electronics equipments adopted to compensate for cur-rent harmonic pollution in electric mains, due to nonlinear loads. By using a proper"floating"capacitor as energy reservoir, the SAF purpose is to inject in the line grid currents canceling the polluting har-monics. Control algorithms play a key role for such devices and, in general, in many power electronics applications. Moreover, systems theory is crucial, since it is the mathematical tool that enables a deep understanding of the involved dynamics of such systems, allowing a correct dimensioning, beside an effective control. As a matter of facts, current injection objective can be straightforwardly formulated as an output tracking control problem. In this fashion, the structural and insidious marginally-stable internal/zero dynamics of SAFs can be immediately highlighted and characterized in terms of sizing and control issues. For what concerns the control design strictly, time-scale separation among output and internal dynamics can be effectively exploited to split the control design in different stages that can be later aggregated, by using singular perturbation analysis. In addition, for robust asymptotic output tracking the Internal Model Principle is adopted.


Introduction
Harmonic pollution in the AC mains determines additional power losses and may cause malfunctioning or even damage to connected equipments. Distortion of the currents circulating on electric mains is mainly originated by non linear loads, as AC/DC uncontrolled rectifiers used for motor drives, that absorb undesired current harmonics. Therefore, local countermeasures have to be taken in order to keep troller devoted to harmonic compensation (the AC/DC boost-based SAF is an underactuated system). This is a crucial point and it has to be tackled preserving harmonic compensation performances as far as possible. In this work a power/current controller, based on Internal Model Principle, (see Marconi et al. (2003), , Marconi et al. (2007)) is designed in order to cancel current harmonics, ensuring robustness with respect to SAF parameter uncertainties. By exploiting the internal model approach, the proposed solution also allows to merge and solve at the same time the two above-mentioned problems of current harmonics isolation and current reference tracking. As regards the robust stabilization of the DC-link voltage internal dynamics, a cascade control structure is proposed. An additional voltage controller, acting on the references of the power/current controller, is introduced. This controller is designed taking into account the structural voltage oscillations required for harmonic compensation and minimizing the impact on harmonic compensation. In particular, by exploiting a proper averaging (Sanders et al., 1991) of the capacitor voltage dynamics, the average value of the capacitor voltage is chosen as output variable to be controlled (Hanschke et al., 2006). As far as the overall stability is concerned, the previously mentioned time-scale separation between portions of SAF dynamics can be effectively exploited to decouple power/current tracking and voltage stabilization control problems, using averaging and singular perturbation theory techniques (Khalil, 1996). This chapter is organized as follows. In Section 2, the general framework is described, the SAF model is derived and the control objectives are formally defined. In Section 3, two methodological approaches are presented for the SAF components sizing. The first one is based on the knowledge of the load currents harmonic spectrum, the values selected for the hardware components are the minimums allowing the SAF to deal with the considered load distortion. Differently, the second approach is related to the maximum current of the AC/DC boost switching devices. In this case the selected components values are the minimums which enable the SAF to compensate for all possible loads giving distorted currents smaller or equal to the switches peak value. In Section 4 both the internal model-based power/current controller and the averaging voltage controller design are presented, stability analysis is carried out relying upon the time-scale separation imposed by the design algorithm; both the power and the voltage subsystem are proven to be asymptotically stable, then practical stability of the overall system is claimed exploiting general results on two time-scale averaged systems (Teel et al., 2003). The effectiveness of the proposed control solution is tested in Section 5 through simulations.

Shunt active filter model and control problem statement
The scheme of the shunt active filter considered in this chapter is reported in Fig. 1, as mentioned in the introduction it is based on a three-phase three-wire AC/DC boost converter, where the main energy storage element is a DC-bus capacitor, while the inductances are exploited to steer the filter currents by means of the converter voltages. The switching devices of the three-leg bridge (also called "'inverter"') are usually realized by IGBTs (Insulated Gate Bipolar Transistors) and free-wheeling diodes. In this work the following notation is used to denote the SAF variables; v mabc =(v ma , v mb , v mc ) T is the mains voltage sinusoidal balanced and equilibrated tern, i m =(i ma , i mb , i mc ) T are the mains currents, i l =(i la , i lb , i lc ) T are the load currents, while i=(i a , i b , i c ) T are the filter currents. L indicates the value of the inductances, and C the DC-link bus capacitor value.

Mathematical model
Considering the inductors dynamics, the filter model can be expressed as where R is the parasitic resistance related to the inductance L and to the cables, v NK is the voltage between the nodes N and K reported in Fig. 1, v(t) is the voltage on the DC-link capacitor, and u 1 = (u x , u y , u z ) T is the switch command vector for the legs of the converter. Since a PWM (Pulse Width Modulation) strategy is assumed to control the inverter, the above-mentioned control inputs can be considered such that u 1i ∈ [0, 1], i = x, y, z. According to the three-wire topology for any generic voltage/current vector x it holds hence, from the sum of the scalar equations in (1) it follows that defining it can be verified by direct computations that For what concerns the state equation relative to the capacitor voltage dynamics, it can be derived considering an ideal inverter and applying a power balance condition between the input and the output of the filter, then replacing (3) into (1), the complete filter model results where the filter currents dynamics have been written in a more compact form with respect to (1), multiplying the current vector by the identity matrix of suitable dimension I 3 . Exploiting equations (3), (5), the system model can be reduced to the standard two-phase planar representation of a three-phase balanced systems (Krause et al., 1995), which can be obtained applying the following coordinates transformation the SAF dynamics expressed in this α − β reference frame become according to the hypothesis of three-phase balanced sinusoidal line, the ideal main voltage tern can be expressed in the above-defined bi-dimensional reference frame as follows where V m is the voltage amplitude and ω m the grid angular frequency. For what concerns the control vector u abc , in this reference frame the eight possible configurations of the switching network (reported in Tab. 1) can be mapped in the α − β plane, obtaining the vertexes and the origin of the feasibility space illustrated in Fig.2, while each point in the hexagon can be obtained as mean value in a PWM period. As it will become clear in the next sections, in order to simplify the control objectives definition and the controller design, it is very useful to adopt a further transformation from the two-phase current variables [i α i β ] T to a two-phase real-virtual (imaginary) power variables defined as where dq T αβ = V m cos(ω m t) sin(ω m t) −sin(ω m t) cos(ω m t) .
In this so-called synchronous coordinate setting, aligned with the mains voltage vector, the model of the SAF is expressed asẋ  where it is further to notice that, since the filter currents, the mains voltage and the DC-link voltage are measurable, the full state (x,v) is available for feedback, moreover the actual control action u = [u x u y u z ] can be determined from u abc , which in turn can be derived from u dq . As regards the load description, the same two-phase real-virtual power representation can be used, in particular following (Akagi et al., 1984), the load currents can be approximated as periodic signals given by the sum of a finite number N of harmonics, with frequencies multiple of f m = ω m /2π. Hence the load currents can be expressed in power variables as where the harmonics amplitudes X ld0 , X lq0 , X ldn , X lqn and phases ψ dn , ψ qn are constants. Since the load currents and the mains voltages are measurable, also the variables (x ld , x lq ) will be considered known and available for control purpose.

Problem statement and control objectives
Roughly speaking the main control objective of the considered SAF is to steer the variables x d , x q , injecting power into the line to compensate for the load harmonics. However the ability of tracking current references relies upon the energy stored in the DC-link capacitor, which is the main power source of the filter, therefore another general objective is to keep the DC-link voltage confined in a suitable region, to avoid overcharge and, at the same time, to ensure the capability to steer the filter currents. On the other hand the ability of maintaining DC-link voltage into a suitable region is strictly related to the power exchanged with the mains, which in turn is affected by the current harmonics to be compensated for. The general control objective is then two-folds; one related to the tracking of current disturbances, the other concerns the voltage internal dynamics stabilization. In this paragraph a precise and feasible control problem is formally defined, recalling the considerations made above, and assuming that a suitable dimensioning, that will be deeply discussed in the next section, has been carried out. Bearing in mind the power variables representation of a generic nonlinear load expressed in (12), it turns out that the only desired load component is X ld0 , since it represents first-order harmonics aligned with the mains voltages, while the remaining part of the real component x ld − X ld0 is an oscillatory signal with null balance over a line period, and the imaginary component x lq represent a measure of the misalignment between mains ideal voltage and load currents (see Mohan et al. (1989)) and do not contribute to the power flow. In this respect, the terms x ld − X ld0 , x lq are undesired components which should be canceled by the injected filter currents, hence ideally the control problem can be formulated as a state tracking problem, for system (10), of the following reference a prefect tracking of this reference would ensure pure sinusoidal mains currents perfectly aligned with the mains voltages. However, this ideal objective is in contrast with the requirement to have a DC-link voltage bounded behavior. In order to formally motivate this claim, consider the steady state voltage dynamics in case perfect tracking of the power reference x * (t) is achieved, after some computations it results the signal εΨ(x * (t)) which drives the integrator is periodic with period T = 1/ f m , and it is composed by the sum of a zero mean value signal εL(d 0 −ẋ * ) T x * , and the signal εL(M(R, L)x * ) T x * which has negative mean value as long as parasitic resistance R or reference x * are not zero. By this, no matter the starting voltage value of the DC-link, the capacitor will be discharged and the voltage will drop, providing a loss of controllability of the system. To avoid this phenomenon, the reference must be revised, taking into account an additional power term, which should be drained from the line grid by the active filter, in order to compensate for its power losses. Following this motivation, and recalling that the unique useful component for the energy exchange is the real part of the power variables, the ideal reference signal (13) is modified as in which ϕ 0 is a solution of the following equation this represents the power balancing condition which guarantees that the internal voltage dynamics in case of perfect tracking of the modified reference x * ϕ 0 is and the right hand side εΨ(x * ϕ 0 ) is periodic with period 1/ f m with zero mean value. A brief discussion is needed for the solutions of equation (16), it has two real positive solutions if the following condition is verified from a physical viewpoint relation (18) set an upper bound on the admissible undesired components which can be compensated and on the parasitic resistance R, however, as typically E md >> R, this condition is not limitative at all. The two solutions of (16) under condition (18) are the first solution, minimizing the power drained from the line grid to compensate the power losses, is the physically most plausible, because the power consumed by parasitic resistances in the filter is usually quite small, hence it will be considered throughout the chapter. The control problem which will be faced in this work can now be precisely stated; the issue is to design the control vector u abc in a way such that the following objectives are fulfilled: A) Given the reference signal x * ϕ 0 defined in (15), asymptotic tracking must be achieved, that is lim it can be verified that the tracking of the modified power reference is potentially achievable keeping the voltage dynamics inside the safe region, only if the zero mean value oscillating component of εΨ(x * ϕ 0 ) is properly bounded, this can be ensured by a suitable capacitor design. In the regulator design, saturation of the actual input u 1 , imposed by PWM strategy, will not be taken explicitly into account, also this approximation takes advantage of a correct sizing methodology; as it will become clear in Section 3, a suitable choice of the DC-link voltage lower bound v m , depending on the currents to be compensated for, has to be made to meet the constraint u 1 ∈ [0, 1], at least when the power tracking error is reasonably small. A further consideration needs to be made on the requirement v(t 0 ) ∈ [v m , v M ]; according to the AC/DC boost converter theory (Mohan et al., 1989), the natural response of the system would lead the DC-link voltage at twice the line voltage peak value, due to the resonant behavior of the LC pair and the freewheeling diodes of the switching bridge. If a proper design has been performed, this value is expected to be greater than the voltage range lower bound v m ; hence, after a transient period, the controller can be switched on having the initial voltage value inside the admissible region as required by objective B. Finally it is further to remark that x * ϕ 0 depends on parasitic resistance R through (16), hence it has to be considered as an unknown variable, to be reconstructed by estimating the power losses by means of a proper elaboration of the DC-link voltage signal.

Shunt active filter sizing methodology
The aim of this section is to present a precise algorithm to properly select the SAF hardware components, two different design objectives are considered, the first is to select the minimal component values dependent on the level of current distortion imposed by the load, while the second is to find the minimum capacitor value necessary to compensate all the possible loads compatible with the maximum current rating of the inverter switching devices. Both the methods are control-oriented, that is they ensure the feasibility of control objectives stated in 2.2 and that control input saturation is avoided under nominal load and line voltage conditions. The proposed design method is based on the model derived in Section 2, a further approximation is considered with respect to equation (6); the inductors are modeled as pure inductance, that is the parasitic resistance R is neglected, while ideal mains voltage tern and converter switches are considered as in the previous section.

Inductance value selection
The inductance value can be selected regardless the loads, hence this part of the design procedure is the same for both the design objectives previously defined. The design criterion is based on the maximum current ripple ∆I M pp allowed for the filter currents; current ripple is a consequence of the PWM technique applied to obtain the reference command value u * abc , it has to be bounded in order to limit high frequency distortion. The actual command vector u abc (t) and filter current i(t) are affected by a ripple component substituting these expressions in the state equation (6) it turns out by simple computation it can be showed that the worst ripple case occurs when the desired command value u * abc is in the middle of a feasibility hexagon side (see Fig. 3). In this condition, assuming that the DC-link voltage has constant value V in a PWM period, the peak to peak current ripple is where the sampling period T s and the PWM frequency f PW M are assumed already set before starting the sizing procedure. If the peak to peak ripple must be bounded by the desired maximum value ∆I M pp , the following inequality needs to be fulfilled the upper bound of the voltage range v M depends only on the kind of capacitor and it can be supposed already chosen before starting the design procedure, hence the minimum inductance value L min compatible with the desired maximum current ripple can be selected applying equation (25).

Load-based approach
Let us now consider the first design algorithm based on the knowledge of the load to be compensated for. The load distortion will be modeled as in equation (12), taking into account the constraint on the maximum current I max of the device implementing the bridge switches. The switching devices sizing depends on the total amount of power (distorted and reactive) P = 3V mRMS I SAFRMS that the filter has to compensate for (if the load is known then P is known), hence by the route mean square value I SAFRMS , the maximum current that the switches need to drain can be readily obtained as I max = √ 2I SAFRMS . The desired filter currents (denoted with * ) necessary to fulfill the tracking objective A defined in 2.2 can be effectively imposed by the converter if each component is less than the maximum allowed value, this feasibility condition can be graphically represented considering that each projection of the filter currents vector must be less then I max , hence the feasibility space is an hexagon similar to that reported in Fig. 4 (obtained taking P = 45kVAR as filter size, V mRMS = 220V and then I max = 70A). Therefore condition (26) can be readily checked considering the inscribed circle in the feasibility hexagon. If the load currents do not satisfy constraint (26) the number of current harmonics to be compensated for has to be reduced, differently, when the filter performance cannot be decreased, the opportunity to connect two shunt active filters to the same load can be considered.
Assuming that an inductance value such that L ≥ L min has been selected, the voltages at the input of the six switches bridge can be calculated as the above equation is obtained by inversion of equation (10) with R = 0 and expressing the model in the synchronous reference frame in current rather than in power variables, in order to directly consider the load currents in the design approach. The constraints on the command inputs need to be considered too, by (27) the inductance value must be as low as possible in order to make u * dq feasible, taking into account also the current ripple limitation we select L = L min . As mentioned, the choice of the of the capacitor voltage lower bound value plays a key role to avoid saturation issues on command inputs, this can be easily verified approximating the hexagon in Fig. 2 with the inscribed circle. In order to avoid control action saturation (assuming perfect power tracking) it must be imposed that with r in the radius of the inscribed circle and v usually v m is oversized with respect the value given by the inequality above, in order to avoid saturation even if non-zero tracking errors are present. If condition (29) cannot be satisfied, some alternatives need to be considered; the capacitor can be changed in order to adopt an higher upper bound v M , when the costs of the project have to be limited and the kind of capacitor cannot be substituted, the number of harmonics considered must be reduced until (29) is satisfied. To preserve the number of harmonics to compensate, the inductance value can be reduced, penalizing the current ripple and then tolerating a greater high frequency distortion. The capacitor value can then be selected assuming an ideal converter and writing the balance equation between the instantaneous reference power at the input of the six switches bridge and the power of the DC-link capacitor, hence the corresponding energy can be calculated as by the hypothesis of sinusoidal load currents and ideal mains voltages E f ilt (t) is periodic of frequency f m and its mean value is zero. Defining and imposing that the voltage variation corresponding to E max is v re f − v m , the capacitor value design equation can be written as

Switches-based approach
As stated at the beginning of this section, a different design method aims to find the capacitor value that makes the filter able to compensate for the worst load compatible with the switches maximum current. If the resulting capacitor value is not too expensive, this method allows to design the filter only knowing the amount of current that has to be compensated. During the optimization procedure the load currents need to be the only varying parameters while all the other values must be fixed. The inductance value is chosen equal to the minimum compatible with the allowed ripple, while the minimum capacitor voltage v m is supposed sufficiently low to make simple the voltage control, and, at the same time, the resulting capacitor value feasible. Writing the filter currents spectrum in the d − q synchronous reference frame, an expression similar to (12) can be obtained the parameters to be varied in order to calculate the worst E max are the (2N + 1) + 1 magnitudes and the 2N + 1 phases, so the following optimization problem has to be solved with respect to the array z of 4(N + 1) + 1 variables, taking into account the following constraints • switches currents must be less than the maximum allowed, that is the current vector must be inside an hexagon similar to that reported in Fig. 4. This can be easily checked approximating the hexagon with its inscribed circle; • the control output must be feasible, that is the vector u abc must be inside the hexagon reported in Fig. 2. This can be easily checked approximating the hexagon with its inscribed circle; • harmonics components phases have to be greater than −π and less than π.
Once E worst max has been determined, substituting its value in (33), the capacitor value relative to the switches-based design approach can be selected. In the discussion above, ideal mains voltages have been assumed, if also the grid line voltages are distorted, the capacitor has to provide more energy to the load, hence its value must be higher than the one calculated under ideal conditions. In case of ideal mains voltages the load instant power is the one calculated in (12) and the only power term that the filter must deliver is x ldn = ∑ N+1 n=1 X ldn cos(nω m t + ψ dn ) = V m i ldn having zero mean value. If the mains voltages are distorted, their representation in the synchronous reference frame is line voltages harmonic perturbation produces additive terms in the load instantaneous power expression, that by direct computation can be written as the above equation shows that the filter has to provide more power to the load, furthermore the power mean value in a PWM period can be different from zero. Hence also assuming that the mean value becomes zero in a finite time, the capacitor must be oversized with respect to the ideal situation, in order to accumulate more energy.

Robust controller design
In this section the control problem defined in 2.2 is addressed, relying upon a suitable capacitor value given by the procedure described in the previous section, the two interlaced objectives A and B defined in 2.2 can be approached individually by exploiting the principle of singular perturbation. Two independent controllers (reported in the block diagram of Fig. 5) will be designed. An internal model-based controller (IMC) is proposed in order to deal with the problem of robust reference tracking (defined in objective A) for the fast subsystems composed by the power variables dynamics, while an independent voltage controller for the slow DC-link voltage subsystem is designed to produce a reference modification η which compensate the unknown power losses term ϕ 0 , allowing to achieve objective B. The averaged voltage value is chosen as the controlled variable, and a phasor variables representation is exploited to design the regulator, this choice allows for the necessary voltage oscillation during nominal operation, and improves the voltage dynamics behavior with respect to other proposed solutions (Marconi et al., 2007). Stability analysis is carried out in two steps; the reduced averaged dynamics, obtained replacing the steady state of the fast subsystem into the slow voltage dynamics and carrying out the average value to obtain a phasor variables representation, and the boundary layer system, obtained considering the SAF currents dynamics and an ideal energy storage element, are proved to be asymptotically stabilized by the proposed controllers. Then practical stability for the overall closedloop error system is stated exploiting well-established singular perturbation and two time-scale systems theory results. Before detailing the proposed control structure, consider the first preliminary control law which is always well defined provided that v(t) ≥ v m > 0 for all t ≥ 0 according to objective B. Replacing (38) into (10) yieldsẋ now consider the modified power reference and define the change of variablesx where V * 2 = (v 2 m + v 2 M )/(2) is the reference value for the square DC-link voltage. Note that the requirement B of having v(t) ∈ [v m v M ] for all t ≥ t 0 can be equivalently formulated in the error variablez requiringz(t) ∈ [−l * l * ] for all t ≥ t 0 , with l * = (v 2 M − v 2 m )/2. The complete system (39) can be then expressed in the error variables defined in (41), the transformed model resultṡx The controller design will be carried out considering the error dynamics in (42), in summary the idea is to steer the closed loop dynamics toward a steady state in whichz is free to oscillate within the admissible region, but its mean value is steered to zero (i.e the DC-link voltage mean value is steered to V * ), andx is steered to zero, i.e the power x follows a reference which is the sum of the term x * , which takes into account the undesired harmonic load components, and a constant bias η which is needed in order to compensate the power losses and to make the range [v m v M ] an invariant subspace for the voltage dynamics.

Averaging voltage controller
In order to fulfill objective B the voltage dynamics need to be stabilized, in this respect the subsystem composed by the capacitor voltage dynamics will be considered, a suitable reduced averaged system will be sought, and then a controller for the capacitor voltage DC component will be designed. The first step is to average the voltage differential equation to obtain the dynamics in the so-called phasor-variables, then, a control law, itself expressed on phasor representation, can be designed following an approach similar to that proposed in (Valderrama et. al, 2001), however in this work the only voltage subsystem is controlled using phasor variables, while the power subsystem is controlled in the real time domain. The controlled variable is chosen to be the time-window averaged valuez a of the square voltage error z, and the averaging is performed over the time interval [t − T ,t]. In terms of (Sanders et al., 1991) this average value is a zero-order phasor defined as the fact thatz a is a zero-order phasor allows to obtain its derivative by simply applying the same averaging procedure to its differential equation in (42) note that the average voltage derivative can also be expressed as the difference over one period of the actual voltage, hence d dt (z a ) = d dt this insight connotes the availability ofz a for measurement in real time, and, as it will later clarified, it is of crucial importance for an actual implementation of the controller. All further elaborations will focus on the integral-differential equation (44) representing the averaged error voltage dynamics. This equation depends onū which is actually provided by the power tracking controller, to eliminateū consider that the differential equation forx in (42) can be rewritten as replacing (46) into (44) the following equation is obtaineḋz whereD(x) collects all the terms depending on the power tracking errorx. The next step is to exploit the fact that the reference term x * is T -periodic (T = 1/ f m ), hence it results in a constant value when averaged over this period, this is a key advantage of the averaging approach for the voltage system. The T -periodic terms in (47) can be summarized to since x * is periodic in T , D * is a constant disturbance, and, due to power losses induced by the parasitic resistance R, it also follows that D * < 0. For further simplification the integral operator can be applied to the occurring derivative terms. Using definitions (11), (40), after some computations the averaged error voltage dynamics can be expressed completely in phasor variableṡz where the following nonlinear term has been defined which enters (49) with its average and its averaged derivative the averaged error voltage system is thus controlled by means of the averaged control input According to singular perturbation theory, the voltage controller design can be carried out considering only the reduced dynamics, obtained confusing the value ofx with its steady state valuex = 0. As previously remarked, this approximation can be introduced thanks to the small value of ε which, multiplying the voltage dynamics in the second of (42), makes the voltage subsystem much slower with respect to the power dynamics in the first of (42) (this phenomenon is usually referred as two time-scale system behavior) that will approach the steady state much faster thenz. Thus reduced voltage dynamics can be obtained by (49) simply dropping the coupling termD, because by definitionD(0) = 0.
The nonlinear terms ν a , andν a cannot be managed easily, beside non-linearity they contain an integral, a time delay and a time-varying term x * d . In order to simplify the mathematical treatment, a sort of linearized version of system (49) will be considered. This linear approximation is motivated by several facts; since the parasitic resistance R and the filter inductance value L are usually very small with respect to the term E md in every realistic setup, nonlinear term are much smaller than the linear ones. Furthermore the component x * d has no influence at all in averaging terms if η is constant, thanks to the fact that it is T -periodic with zero mean value. Hence it will influence the averaged system only while η is varying, and also in this case its oscillatory part will be filtered by the averaging procedure. As a result of the previous steps and considerations, the linearized averaged model for the reduced dynamics can be written as˙z where, as mentioned, ϕ 0 is the smallest solution of equation (16). Now it is possible to design the control input η a in order to stabilize the origin of system (53), a standard PI regulator in the averaged variables is proposed it is further to notice that the ε factor in the integral action of the controller is introduced to keep the voltage controller speed in scale with the voltage subsystem to control, thus maintaining the two-time scale behavior of the overall system. In order to prove the asymptotic stability of the closed-loop system resulting by the interconnection of (54) and (53) consider the change of coordinatesθ = θ − ϕ 0 , which results in the closed-loop error dynamics d dt since ε, E md are positive, the matrix in (55) is Hurwitz for all K P > 0, K I > 0, and system (55) result asymptotically stable despite the unknown disturbance ϕ 0 . The problem with implementing the regulator (55) is that the resulting control signal is the average value of the actual control input η, thus some procedure is required to synthesize a real-world control signal whose mean value satisfies the above conditions. In the SAF specific case this problem can be solved, consider the derivative of signal η a d dt it can be rewritten on the left side as the difference over one period, while the right side is replaced with the derivative of η a expressed in (54); solving for η(t) yields using (45), the derivative of the averaged square voltage error is actually measurable, thus the above formula is implementable. However, while the interconnection between voltage subsystem and controller is stable in sense of the averaged value, a further step is required. In the incremental implementation (58) there is no more an integral action, the control input history is kept in memory for one period, still the controller provides stability for the averaged voltage errorz a . Consider now that for the phasor variables system, a stable steady-state guarantees that all the variables have a constant average value, while being allowed to oscillate freely. This property is desired for what concern the capacitor voltage and it is the main motivation for applying the averaging procedure, however implementation according to (58) can introduce undesired periodic oscillation in the control input η, moreover oscillation will persist being remembered through the time delay term. In summary, while η a will approach the constant power loss value ϕ 0 , the actual input η might be any periodic signal with average value equal to ϕ 0 . Recalling that η modifies the real power reference value x * d , any oscillation will result in a non-zero error for the power tracking controller. In order to avoid this situation the following term can be added to (58) the reason of this modification is to cancel the oscillations stored in memory, by correcting the stored signal towards its own mean value η a (t − T /2). It is important to remark that the averaged value is not the actual mean value of its corresponding signal, the mean value s m of a signal s(t) is defined as the above equation is identical to the zero-order phasor definition, except for a time shift of T /2. For this reason the mean value of the stored signal η(t − T ) has been expressed as its time shifted average value, note that the mean value of this stored signal can be computed because also its "future" values are available. The additive term d η is a zero mean value signal, because it is obtained removing its DC-value to a periodic signal. Since the control input η enters the averaged system (55) after being averaged itself, any modification having zero mean value will not affect the behavior of the averaged system dynamics. Hence the final implementation of control input together with (59) is this controller will not introduce undesired oscillation because it depends solely on averaged signals, whose simplified dynamics (55) cannot give oscillations.

Power tracking controller
The voltage controller output reported in (61) can be replaced into the filter error power dynamics in (42), recalling also equation (54), it turns ouṫx where is a T-periodic term composed by the sum of a constant term and sinusoids having known frequency, while f (z a ,θ ,ż a ,˙θ , ε) = T K pza + εK Iża The problem of forcingx in (62) clearly requires the ability of the control law to compensate for the signal d(t), perfect tracking cannot be achieved by a feedforward action since SAF parameters and d(t) are not fully known. To comply with uncertainties and provide robustness we propose an internal model-based controller. Each component of the vector d(t) can be seen as the output of the following linear systemẇ where Γ i ∈ R (1×2N+1) are suitably defined vectors and matrix Ω ∈ R (2N+1)×(2N+1) is defined as Ω = blkdiag(Ω j ) with Ω 0 = 0 and with the pairs (Γ i ,Ω) observable. Defining Φ = blkdiag(Ω, Ω) and Γ = blkdiag(Γ d , Γ q ), the following internal model-based controller can be designeḋ where matrices Q and K need to be properly assigned. Once chosenū as in (67) and defined the internal model error variables asξ = ξ − Lw, where w := [w T d , w T q ] T , the power subsystem closed-loop error dynamics can be rewritten aṡx According to the general two time-scale averaging theory, the power tracking problem can be studied focusing on the boundary layer system, obtained by putting ε = 0 into the overall error dynamics, hence by (47), (54) andż a = 0,˙θ = 0, thus system (68) becomeṡx Now matrices K, Q need to be selected such that asymptotic stability is provided for the boundary layer system. Define two arbitrary Hurwitz matrices F d , F q ∈ R(2N + 1) × (2N + 1), and two arbitrary vectors G d , G q such that the pairs (F d , G d ), (F q , G q ) are controllable, taking the controller matrices as with k d , k q two arbitrary positive scalars, k a positive design parameter, and E d , E q defined as nonsingular solutions of the following Sylvester equations: asymptotic stability of the boundary layer system can be stated. In order to prove this claim let us define the vector where Γ d1 , Γ q1 denote the first element of vectors Γ d , Γ q respectively and 0 2N is a zero raw vector having dimension 2N. Consider now the change of variables where F = blkdiag(F d , F q ). Using standard linear system tools it can be verified that a valuek exists, such that ∀ k ≥k the state matrix of the system in the new coordinates is Hurwitz, hence asymptotic stability of the boundary layer system can be stated.

Overall system stability
Asymptotic stability has been stated for the boundary layer system and a linearized version of the averaged reduced voltage dynamics. Exploiting the main results of the two time-scale averaged systems theory, it can be proved that the two separately designed power and DC-bus voltage controllers, are able to provide practical stability for the complete system (42), that is it's possible to claim that there exists a value ε * , such that ∀ε < ε * , k ≥k, l ≤ l * the set is practically stable (Khalil, 1996) for the closed-loop trajectories of the complete error system. The fact that the proposed regulator is able to achieve the control objectives in a practical way means that the power vector x can be steered arbitrary close to the reference value x * ϕ 0 while the averaged value η a tends arbitrary close to the power loss term ϕ 0 . It's further to notice that the asymptotic tracking error can be arbitrary reduced by taking a smaller value for ε, that is by increasing the capacitor value C.

Simulation results
Simulation tests have been performed in order to validate the proposed control solution. Two different scenarios have been adopted; first model (6) has been implemented in MATLAB/Simulink and a load scenario with two harmonics at 7ω m and 13ω m has been chosen. Then, in order to validate the controller performance in a situation closer to a real setup, the proposed continuous-time regulator has been discretized adopting a sampling frequency f s = 7 KHz, then the SAF converter components have been modeled by using Simulink/SimPowerSystems toolbox, and a suitable PWM technique with a carrier frequency equal to f s has been implemented. Finally a three phase diode bridge has been selected as nonlinear load scenario. The following system parameters has been set, according to the procedure illustrated in Section 3; C = 4400µF, L = 3.3mH, R = 0.12Ω, while the DC-link voltage limits have been set to v m = 700V , v M = 900V . Ideal three-phase mains voltages with amplitude V m = 310V and frequency f m = 50Hz have been modeled. The internal-model based controller has been tuned to the load disturbances, according to the procedure described in 4.2, for what concern the simulations in time continuous domain. As regards the diode rectifier load scenario, the most relevant power disturbances, that is the 6 th and the 12 th load current harmonics expressed in the synchronous d − q reference frame (corresponding respectively to the 5 th and the 7 th , and to the 11 th and the 13 th in the fixed reference frame), have been considered, then the IMC controller has been discretized according to the procedure reported in , thus the following matrices have been selected; Ω = blkdiag(Ω 0 , Ω 6 , Ω 12 ), Γ d = Γ q = (1, 1, 0, 1, 0) T , K = diag (200,200) and Q = 10 3 diag(Q d , Q q ), where Q d = Q q = (40. 6, 80.7, 7.15, 78.7, 17.6) T . For what concerns the voltage stabilizer described in 4.1, the following parameters have been selected K P = 0.3, K I = 3.7. Consider now the performance obtained on the first simulation scenario, with ideal SAF model and the 7 th , 13 th disturbance harmonics; in Fig. 6 the tracking error on both real and imaginary power variables is reported, as expected, asymptotic perfect tracking is achieved and the vectorx is steered to the origin. This ideal behavior is confirmed by Fig. 7, 8; the two harmonics currents are totally canceled out by the filter currents, while a small current component oscillating at the first-order harmonic frequency and aligned to the corresponding voltage, arises on the line side due to the voltage controller action. In For what concerns the voltage controller, in order to validate the stability properties, a value quite far from the mean voltage reference value (v 2 m + v 2 M )/2 = 800 V has been chosen as initial condition for the capacitor voltage. As showed in Fig. 9, even though the average value is initialized at zero and needs one period before representing the actual voltage, the voltage controller reacts immediately, thanks to its dependance on the averaged derivativeż a . Hence the voltage averaged error is successfully steered to zero, and the capacitor voltage is brought back to the middle of the safe interval, without exceeding the upper and lower bounds. The initial nonlinear behavior of the voltage error trajectories is originated by the neglected nonlinearities and also by the coupling termD(x), although it has been neglected due to two time-scale behavior hypothesis, it's excited by the internal model controller transient when harmonics compensation starts. As regards the second simulation scenario, carried out in discrete time domain and with a more detailed filter physical model, the power tracking performance are reported in Fig. 10, 11, 12, in this case the power error variablesx d ,x q are not exactly zero, due to the fact that AC/DC rectifier high order harmonics are not compensated by the internal model, furthermore the discretization effects have to be taken into account. However the load currents harmonics for which the controller has been tuned are strongly reduced at the line side as the currents magnitude spectrum reported in Fig. 12 shows. Analyzing the currents waveform in the time domain (Fig. 11), it can be verified that the mains currents are almost sinusoidal and perfectly aligned with the corresponding phase voltages, hence also the load imaginary power is almost totally compensated. The ripple introduced by the pulse with modulation can be noted on the filter current, it affects also the mains currents, however thanks to a correct inductance sizing, the high frequency distortion is properly bounded. Quantitative performance of the powertracking controller obtained with this scenario are summarized in Tab. 3. The current component corresponding to the line frequency oscillation is slightly larger at the line side than at the load side, due to the additional active power drained to compensate for the filter losses. As regards the averaging voltage controller, a discrete time version has been implemented, while the same initial conditions of the first scenario have been reproduced. In Fig. 13

Conclusions
In this chapter a nonlinear robust control solution for a shunt active filter has been proposed, the focus has been firstly put on the hardware components design issue, providing a suitable algorithm, based on the structural system properties, which gives guarantees on the feasibility of the control problem and allows to obtain a crucial time-scale separation between the power and voltage dynamics. Then exploiting nonlinear systems analysis well established tools, such as averaging and singular perturbation theory, an averaging capacitor voltage controller and a power tracking controller based on the internal model principle, have been presented. The former exploits the insight that, regulating the averaged voltage value, makes it possible to ignore the necessary oscillations for a proper filter operation, and improves the voltage dynamics behavior. The second is chosen in order to ensure asymptotic tracking of undesired load current components, providing also robustness with respect to disturbances and model uncertainties. Saturation issues have not been explicitly addressed in this work, owing to space limitation, however it is of utmost importance to deal with these phenomena for an actual industrial implementation with stability and performance guarantees. Some solutions, for the SAF specific case, have been proposed (see , ), however this is still an open research topic. Future effort will thus be devoted to improve the filter performance under control input saturation, analyzing the problem in the context of modern anti-windup approaches, hence providing a rigorous characterization of the system under saturation constraints. Moreover discretization issues relative to the nonlinear controller here discussed will be further analyzed, in order to improve the discrete-time controller performance with respect to that obtained applying standard discretization techniques.