Cascaded NPC/H-Bridge Inverter with Simplified Control Strategy and Superior Harmonic Suppression

In recent decades the electric power systems has suffered significant power quality problems caused by the proliferation of non linear loads, such as arc furnace lighting loads adjustable ac drives etc., which causes a large amount of characteristic harmonics, low power factor and significantly deteriorates the power quality of the distribution system (Benslimane, 2007; Franquelo et. al., 2008; Gupta et al., 2008). The increasing restrictive regulations on power quality have significantly stimulated the development of power quality mitigation equipments. For high power grid connected systems, the classical two level or three level converters topology are insufficient due to the rating limitations imposed by the power semiconductors (Holmes & McGrath, 2001; Koura et al., 2007). Hence considerable attention has been focused on multilevel inverter topologies. This important multilevel technology has found widespread application in medium and high voltage electric drives, renewable energy – grid interface, power conditioning, and power quality application (Lai & Peng, 1996; Peng et al., 1996; Rodriguez et al., 2002; Sinha & Lipo, 1996; Tolbert et al., 1999). Multilevel converters offer several advantages compared to their conventional counterparts (Manjrekar & Lipo, 1988, 1998, 200; Corzine & Familiant, 2002; Lund et. al., 1999; Sneineh et. al., 2006; Park et. al., 2003; Zhang et al., 2002; Ding et. al., 2004; Duarte et al., 1997; Rojas &. Ohnishi, 1997). By synthesizing the AC output terminal voltage from several voltage levels, staircase waveforms can be produced, which in their turn approach the sinusoidal waveform with low harmonic distortion, thus reducing filters requirements. However the several sources on the DC side of the converter make multilevel technology difficult to control by the need to balance the several DC voltages. For the class of multilevel inverter called diode clamped, if a higher output voltage is required one of the viable methods is to increase the number of inverter voltage levels. For Neutral Point Clamped (NPC) inverter voltage can only be increased up to five level beyond which DC voltage balancing becomes impossible. For single Phase H Bridge inverter, an increase in the number levels leads to increase in the number of separate DC sources, thus the proposed hybrid model is developed by combining the NPC and Hbridge topologies (Wu et al., 1999).


Introduction
In recent decades the electric power systems has suffered significant power quality problems caused by the proliferation of non linear loads, such as arc furnace lighting loads adjustable ac drives etc., which causes a large amount of characteristic harmonics, low power factor and significantly deteriorates the power quality of the distribution system (Benslimane, 2007;Franquelo et. al., 2008;Gupta et al., 2008).The increasing restrictive regulations on power quality have significantly stimulated the development of power quality mitigation equipments.For high power grid connected systems, the classical two level or three level converters topology are insufficient due to the rating limitations imposed by the power semiconductors (Holmes & McGrath, 2001;Koura et al., 2007).Hence considerable attention has been focused on multilevel inverter topologies.This important multilevel technology has found widespread application in medium and high voltage electric drives, renewable energy -grid interface, power conditioning, and power quality application (Lai & Peng, 1996;Peng et al., 1996;Rodriguez et al., 2002;Sinha & Lipo, 1996;Tolbert et al., 1999).Multilevel converters offer several advantages compared to their conventional counterparts (Manjrekar & Lipo, 1988, 1998, 200;Corzine & Familiant, 2002;Lund et. al., 1999;Sneineh et. al., 2006;Park et. al., 2003;Zhang et al., 2002;Ding et. al., 2004;Duarte et al., 1997;Rojas &. Ohnishi, 1997).By synthesizing the AC output terminal voltage from several voltage levels, staircase waveforms can be produced, which in their turn approach the sinusoidal waveform with low harmonic distortion, thus reducing filters requirements.However the several sources on the DC side of the converter make multilevel technology difficult to control by the need to balance the several DC voltages.For the class of multilevel inverter called diode clamped, if a higher output voltage is required one of the viable methods is to increase the number of inverter voltage levels.For Neutral Point Clamped (NPC) inverter voltage can only be increased up to five level beyond which DC voltage balancing becomes impossible.For single Phase H Bridge inverter, an increase in the number levels leads to increase in the number of separate DC sources, thus the proposed hybrid model is developed by combining the NPC and H-bridge topologies (Wu et al., 1999).
A lot of research has been done on single phase H-Bridge inverter where each inverter level generate three different voltage outputs, +V dc , 0, and -V dc by connecting the dc source to the ac output using different combinations of the four switches of the Bridge (Peng et al., 1996).There has also been more emphasis on modeling and control of a five level NPC/H-bridge inverter without cascading the bridge (Cheng & Wu, 2007).This fails to address the principle of realizing a general cascaded n-level NPC/H-Bridge.It is on this need of realizing a higher voltage output with simplified control algorithm that this book chapter proposes a simplified control strategy for a cascaded NPC/H-bridge inverter with reduced harmonic content.Because of the modularity of the model only two cascaded cells which gives a 9 level cascaded NPC/H-bridge inverter is considered.The new control strategy is achieved by decomposing the nine level output into four separate and independent threelevel NPC PWM output.By combining the three-level NPC PWM back to back using DC sources and properly phase shifting the modulating wave and carrier a simplified control strategy is achieved with reduced number of components.The control strategy is applied on cascaded NPC/H-bridge inverter that combines features from NPC inverter and cascaded H-Bridge inverter.For higher voltage applications, this structure can be easily extended to an n-level by cascaded NPC/H-Bridge PWM inverters.The article starts by developing a control algorithm based on novel phase shifted PWM technique on the proposed inverter model.This is done on a two cell of the cascaded model to realize nine level voltage output.A theoretical harmonic analysis of the model with the proposed control algorithm is carried out based on double Fourier principle.Spectral characteristics of the output waveforms for all operating conditions are studied for a fivelevel and nine-level voltage output.Theoretical results are verified using MATLAB simulation.The results shows that the spectrum can be made to only consist of the multiples of fourth order for a five level and with proper phase shift combination, a multiple of eighth order is achieved for nine level voltage output.The results are compared with those of a conventional multicarrier PWM approach; it is shown that with the proposed phase shifted PWM approach, the inverter exhibits reduced harmonic content are present.Finally the article compares the components count of the the model with the convetional cascaded Hbridge inverter, it is clealry shown that the proposed model requires a lesser number of separate dc sources as compared to conventional cascaded H-bridge inverter.

Main system configuration
Fig 1 shows the circuit configuration of the proposed nine-level cascaded NPC/H-Bridge PWM inverter which consists of two legs for each cell connected to a common bus.Four active switches, four freewheeling diodes and two diodes clamped to neutral are adopted in each leg.The voltage stress of all the eight power switches is equal to half of DC bus voltage.The power switches in each leg are operated in high frequency using phase shifted PWM control technique to generate the three voltage levels on the ac terminal to neutral voltage point The building block of the whole topology consists of two identical NPC cascaded cells.The inverter phase voltage V an is the sum of the two cascaded cells, i.e., Assuming that the two capacitor voltages on the DC bus voltage are equal, five different voltage levels +2Vdc, +V dc , 0, -V dc and -2V dc , are generated on the ac terminal V 01 which consist of two legs.Same applies to V 02 fig. 2 shows the switching model for a nine-level output [6].This implies that by cascading two NPC/H-Bridge inverters (V 01 and V 02 ) and properly phase shifting the modulating wave and carriers, a nine-level PWM output is achieved.The number of output voltage levels is given by Where N is the number of series connected NPC/H-Bridges.The topology is made up of four three level legs and each leg has four active switches and four freewheeling diodes.

System operation
Most of the past research on modeling of cascaded multilevel inverter has concentrated on realizing a switching model of conventional H-bridge inverter without giving a guideline Fig. 2. Operating modes of one cell of NPC/H-Bridge inverter on how one can get operating modes of cascaded NPC/H-bridge inverter and hence obtain a valid model for the topology.This section analyses eight valid operating modes of one cell of the proposed topology.The following assumptions are made in the modeling and analysis process: • All components (power switches and capacitors) are ideal.

•
The DC-link capacitors V 1 , V 2 , V 3 and V 4 have the same capacitance.

•
PV cells supplies constant and equal voltages to the four DC link capacitors.

•
The reference phase voltage is assumed to be a constant value during one switching period.Figure 3 shows the operation modes for one NPC/H-bridge cell from the 9-level inverter.In mode 1 the power switches S 11 & S 12 and S 23 & S 24 are turned on to supply voltage at the output of first NPC/H-bridge cell that is equal to V 01 = V 1 + V 2 .The capacitors C 1 and C 2 are discharged as they supply power to the utility as shown in figure 2 (a).The modes 2 to 8 are as shown in figures 2 (b) to 2 (h) respectively.In mode 2 the output voltage is Based on the analysis of the operation model, the state variable equation for the proposed inverter can be estimated.To prevent the top and bottom power switched in each inverter leg from conducting at the same time, the constraints of power switches can be expressed as: Where i = 1, 2. Let's define the switch operator as: T 1 = S 11 & S 12 ; T 2 = S 13 & S 13 ; T 3 = S 21 & S 22 T 4 = S 23 & S 24 .The four valid expressions are given by: From fig. 4 taking two legs for each cell to be a and b, the equivalent switching function are: Using equation (3 -7), a switching state and corresponding voltage output V o1 can be generated as shown in table 1 which clearly indicates that there are 8 valid switching states; From table 1, the voltage V 01 generate by the inverter can be expressed as: For the control technique stated above; the voltage level for one leg of the cell is given as: Table 2. Switching scheme for one phase leg of a nine level cascaded NPC/H-bridge inverter From equation ( 9), the voltage output for one cell of the model can be deduced as; For the compound nine level inverter let's assume that V 1 = V 2 = V 3 = V 4 = V, the switching states are as shown in Table 2.For a nine level cascaded NPC/H-bridge inverter, there are 22 valid switching states though two of the switching states are short circuits and thus cannot compensate the DC capacitor as current do not pass through either of the four DC-link capacitors.

Mathematical analysis
Most of the past research on modeling of cascaded multilevel inverter has concentrated on realizing a switching model of conventional H-bridge inverter without giving a guideline on how one can get operating modes of cascaded NPC/H-bridge inverter and hence obtain a valid model for the topology.This section analyses eight valid operating modes of one cell of the proposed topology and proposes an equivalent circuit for the topology.
The following assumptions are made for deriving the mathematical model of the cascaded H-bridge inverters.

•
The grid is assumed to be AC current source,

•
The power losses of the whole system are categorized as series loss and parallel loss.
The series loss and interfacing inductor loss are represented as equivalent series resistance (ESR).Parallel losses are represented as shunt connected resistances across the dc-link capacitors.The differential equations describing the dynamics of the coupling inductor between the NPC/H-bridge inverter and the grid of the model shown in fig. 1 can be derived as: According to Kirchhoff's law, the currents flowing into the dc link capacitors C 1 and C 2 can be expressed as: The equations ( 13) and ( 14) can be rearranged as: Equation ( 16) can be written in the format of: Capacitor current, inverter current and utility line current and DC-Link capacitors are taken as state variables: 12 1 2 1 2 000 0 01 0 0 0 00 0 0 00 0 00 0 0 Matrix A depends on each operating mode as such Considering the same assumption made earlier that the dc link capacitors have the same capacitance , the state space equation ( 17) can be simplified to: '' ' Where k depends on the operating mode and can take five different values: 1. 0.5 0, -05, -1.

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For a three phase system, V s is replaced V s (cosω o t), V s (cosω o -2π/3) and V s (cosω o +2π/3.similarly the Z, A and B matrices are expanded accordingly to three phase.Where V s is the grid voltage.

Harmonic analysis of a nine level cascaded NPC/H-bridge inverter
Having realized a nine-level output from the a cascaded 9-level model, it is important to theoretically investigate its harmonic structure and show how harmonic suppression is achieved.Based on the principle of double Fourier integral (Holmes & Thomas, 2003).the first modulation between triangular carrier v cr1 , and the positive sinusoidal waveform a naturally sampled PMW output V p (t) of equation ( 30).Where M is the modulation index, V dc is the DC link voltage of the PWM inverter and J n is the n th order Bessel function of the first kind.Using v cr2 which is the same carrier but displaced by minus unity, the naturally sampled PWM output V n is as given in equation ( 31) The output of leg 'a' is given by V a (t) = V p (t) -V n (t) which is: The output of leg 'b' is realized by replacing ω s with ω s + π and using v cr2 which is same as phase displacing v cr1 by minus unity which gives From equations ( 32) and ( 33), it can be clearly deduced that that odd carrier harmonics and even sideband harmonics around even carrier harmonic orders are completely eliminated.Five-level obtained by taking the differential output between the two legs and is given by (35).Similarly the output between the other two legs of the second cell of the hybrid model is achieved by replacing ω s with ω s + π and ω c with ωc + π/4 which gives another five level inverter for equation given by equation ( 34) Equations ( 34) and ( 35) clearly show that for five-level inverter, the proposed control strategy has achieved; Suppression of carrier harmonics to multiples of four; Elimination of even side harmonics around multiples of four carrier harmonics of Multiples of four carrier harmonics.Finally the output for a nine level is achieved differentiating the output voltage between the two cells of the five level cells and this is given by equation ( 36).It can be concluded that for a cascaded N-level inverter the carrier harmonic order is pushed up by factor of 4N where N is the number of cascaded hybrid inverters.The output voltages and spectral waveforms to confirm the validation of the control strategy using this approach of double Fourier transform will be discussed later.

Proposed hybrid control method
The above section has illustrated in general the switching technque for one cell of the cascaded NPC/H-bridge model, because of the modularity of the model, two cells will be considered for modulatin and analysis in this section.For the two cells an improved strategy for realizing nine level output is proposed in this book chapter.The article uses the principle of decomposition where each leg is treated independently and gives a three level output (Naderi &. Rahmati, 2008).Positive and negative legs are connected together back to back and they share the same voltage source V dc .PD modulation is used for achieving three level output (Rodriguez et al., 2002).To achieve a five level PWM output two triangular carriers V cr1 and V cr2 in phase but vertically disposed and modulating wave phase shifted by π are used.The multilevel converter model is modulated using phase shifted PWM technique as illustrated in fig. 3 and 4 for the two NPC/H-Bridge cells.Finally a nine-level PWM output is achieved by using the same two carriers but phase shifted by π/4 and modulating wave phase shifted by π as shown in fig. 5.This is a simple control strategy that can be easily implemented in a digital signal processor.The switching states for one phase leg of a nine-level NPC/Hbridge inverter is shown in table 2, as can be seen there several redundant states which can be utilized in DC voltage balance, this is not within the scope of this paper.The control strategy has two advantages as compared to multicarrier PWM approach (Holmes & McGrath, 2001).First for an N-level cascaded NPC/H-bridge PWM inverter, we can use a switching frequency of 4N times less to achieve the same spectrum as multicarrier approach.This has an advantage of reducing the switching losses, which is an important feature in high power application.Secondly the multicarrier PWM approach requires 8 carriers to achieve nine level output, but the proposed control strategy requires only one carrier phase shifted by (N-1)π/4 where N is the number of series connected NPC/H-Bridge inverter.

MATLAB simulation
Part of the Matlab simulation has already been carried out in section 4 to investigate the proposed phase shifted PWM control technique.In order verify that a nine-level output is achieved by cascading two NPC/H-Bridge PWM inverter and properly phase shifting the carrier and the modulating wave, a model as shown in fig.6 was developed and simulated in MATLAB.The control strategy to minimize harmonics was designed and developed in MATLAB as shown in fig.7 (wanjekeche et.al., 2009).It is assumed that the dc voltage input for each module is E = 1OOV.The inverter operates under the condition of f m =50HZ, m f =20 for a five level output and m a =0.9.The device switching frequency is found from f sw,dev = m f /2 X f m =500HZ www.intechopen.com

Simulation results and discussion
Five-level inverter output are shown in figs.8, 9 and 10 for various switching frequency.Fig. 8 shows the simulated waveform for the phase voltage V 01 of the NPC/H-Bridge PWM inverter and its harmonic content.The waveform V 01 is a five voltage levels, whose harmonics appear as sidebands centered around 2m f and its multiples such as 4m f , 6m f .This simulation verifies analytical equation ( 34) which shows that the phase voltage does not contain harmonics lower than the 31 st , but has odd order harmonics (i.e.n=±1±3±5) centered around m=4, 8, 12.  Fig. 11 shows the waveform of the phase voltage of a nine level NPC/H-Bridge PWM inverter.It has sidebands around 4m f and its multiples, this shows further suppression in harmonic content.This topology operates under the condition of f m =50HZ, m f =40 and m a =0.9.The device switching frequency is found from f sw,dev = m f /4 X f m =500HZ.This simulation verifies analytical equation ( 36) which shows that the phase voltage does not contain harmonics lower than the 67 th , but has odd order harmonics (i.e.n=±1±3±5) centered around m=8, 16, 32.As can be seen from fig. 12, a switching frequency of 1KHZ which fits most of high power switching devices has a THD of 0.18% this makes the topology a perfect fit for most high power application such as utility interface power quality control and Medium Voltage drives.

Comparison of the proposed control technique with conventional PWM multicarrier approach
As can be seen from fig. 1, to achieve the same voltage levels N for each phase, only (N-1)/4 separate dc sources are needed for one phase leg converter of the cascaded NPC/H-bridge model, whereas (N-1)/2 separate voltage voltages is need for cascaded H -bridge inverter.Thus for an n-cascaded NPC/H-bridge inverter, the number of separate DC sources S is given by: 1 4  13 (a) where Phase Disposition and Phase shifted PWM modulation strategy is adopted (Jinghua & Zhengxi, 2008).This is beacuse with conventional PWM multicarrier approach, optimum harmonic cancellation is achieved by phase shifting each carrier by (i-1)π/N (Holmes & Thomas, 2003).where i is the i th converter, N is the number of series -connected single the multicarrier PWM approach requires 8 carriers to achieve nine level output, but the proposed control strategy requires only one carrier phase shifted by (N-1)π/4 as stated in section 4.1 (Wanjekeche et al., 2009).

Conclusion
In this chapter it has been demonstrates with proper modeling of the converter, the operating characteristic and the control technique to be applied on the model can be easily found.This can be used to develop standard model for cascaded NPC/H-bridge inverter which is currently not available.
The article has developed an improved topology that can be used to achieve a nine-level NPC/H-Bridge PWM inverter.It has been clearly shown that five level NPC/H-Bridge inverter that has been proposed by many researchers gives a higher THD which is not acceptable in most high and medium power application unless a filter is used.And since there is limited research on cascaded this important hybrid model, the chapter has developed a novel phase shifted PWM control technique that was tested on a two cell cascaded NPC/H-bridge model.In the proposed control technique it has been shown that by properly phase shifting both the modulating wave and the carrier, a nine-level voltage output can be achieved with a reduced harmonic content.With a THD of 0.18% without a filter, this makes the control strategy for a cascaded nine level NPC/H-bridge inverter a good option for medium and high power application such as utility interface and medium drives.
The simulation results obtained clearly verifies the analytical equations from double Fourier transform, showing that a nine-level output has multiples of eighth-order cross modulated harmonics.From the mathematical analysis it has been shown that cross modulated harmonics for a generalized m-level cascaded NPC/H-Bridge inverter is a multiple of 4N where N is the number of series connected NPC/H-Bridge inverter And finally the superiority of the proposed phase shifted PWM control technique is validated by comparing its waveform spectra with that of the conventional phase shifted PWM technique and it was shown the inverter exhibits reduced harmonic content

Superposed output
Voltage harmonics

Fig. 1 .
Fig. 1.Schematic diagram of the proposed cascaded NPC/H-bridge inverter model www.intechopen.comCascadedNPC/H-Bridge Inverter with Simplified Control Strategy and Superior Harmonic Suppression 243 Fig. 3. (a) PWM scheme and (b) output voltage waveform for one cell of NPC/H-Bridge inverter

Fig. 7 .
Fig. 7. Control strategy for a nine-level cascaded NPC/H-bridge inverter Figs. 9 & 10 shows five-level NPC/H-Bridge inverter output for device inverter switching frequency of 1000HZ and 200HZ respectively.

Table 1 .
Switching States and Corresponding Voltage(s) for One Cell of NPC/H-bridge Inverter

Table 3
shows comparison on the number of components for various multilevel inverters, cascaded NPC/H-bridge inverter requires 16 switching devices just as the other topologies but used only two carriers for any level of voltage output.For comparison between the two cascaded inverters it is readily shown in table 4 that the NPC/H-bridge inverter has an advantage of realizing the same voltage level as cascaded H-bridge inverter with a half number of separate DC sources which is more expensive as compared to clamping diodes.

Table 4 .
Component comaprison for different multilevel inverters for nine level voltage output

6.1 Comparison of the MATLAB simulation results of the two PWM control methods To
clearly investigate the superiority of the model under the proposed PWM control technique, Matlab simulation results was carried out on a cascaded NPC/H-bridge nine level inverter model under the conditions of f m =50HZ, fc =1000Hz and m a =0.9.With the proposed Phase -shifted PWM technique, there is further harmonic suppression as shown in fig.13 (b), as compared to conventional PWM Phase shifted approach.This is clearly illustrated in fig.