Truth table for the proposed switch circuit.
In this chapter, we discuss the compute-in-memory memristive architectures and develop a 2M1M crossbar array which can be applied for both memory and logic applications. In the first section of this chapter, we briefly discuss compute-in-memory memristive architectural concepts and specifically investigate the current state off the art composite memristor-based switch cells. Also, we define their applications e.g. digital/analog logic, memory, etc. along with their drawbacks and implementation limitations. These composite cells can be designed to be adapted into different design needs can enhance the performance of the memristor crossbar array while preserving their advantages in terms of area and/or energy efficiency. In the second section of the chapter, we discuss a 2M1M memristor switch and its functionality which can be applied into memory crossbars and enables both memory and logic functions. In the next section of the chapter, we define logic implementation by using 2M1M cells and describe variety of in-memory digital logic 2M1M gates. In the next section of the chapter, 2M1M crossbar array performance to be utilized as memory platform is described and we conceived pure memristive 2M1M crossbar array maintains high density, energy efficiency and low read and write time in comparison with other state of art memory architectures. This chapter concluded that utilizing a composite memory cell based on non-volatile memristor devices allow a more efficient combination of processing and storage architectures (compute-in-memory) to overcome the memory wall problem and enhance the computational efficiency for beyond Von-Neumann computing platforms.
- logic design
In general, memory devices are considered as one of the most important primitives in every computing system. Although, they play an undeniable role in conventional computers, which the processing units and memory are separate, it is generally believed that future computers, unlike von Neumann architectures, will have a compute-in-memory (CIM) structure. According to Moore’s Law and fundamental VLSI limitations, CMOS technology is expected to face constraints and serious challenges at each technology node . These challenges require solutions both short-term and long-term solving technical and strategic difficulties on Moore’s Law way. Accordingly, researchers both in academia and industries are working hard on different available options and solutions from device up to architecture levels proposing incremental as well as revolutionary approaches. Regarding to this requirements, many efforts and initiatives have done by researches in order to keep on progress in the emerging memory technologies such as Ferroelectric Random Access Memory (FeRAM) , Magnetic Random Access Memory (MRAM) , and Resistive Random Access Memory (RRAM) , etc. Among all these technologies RRAM (generally referred as memristor) has received a lot of attention not only because of its favorable characteristics of low operating voltage, high speed, simple structure, and nano-scale but also with its logic implementation capabilities of the memristor devices. Memristor first in 1971, was proposed by Chua as a non-linear passive element , and then almost 37 years later, in 2008, was physically realized by the HP company, which was fabricated utilizing a Pt–TiO2–Pt structure . These nano-devices are based on a resistor with6variable resistance which can maintain resistance value upon bias removal that can be used as non-volatile memory cells. In addition to the conventional usage as memory cells, this device has also found variety of interesting applications such as machine learning platforms [7, 8], logic circuits design [9, 10], and neuromorphic systems . Considering memristor as a non-volatile memory device makes it an interesting building block for large scale non-volatile memory systems. The memristor, or memory resistor, has been used in crossbar array architectures .
Due to the structural limitations (e.g. sneak path problems, interconnect resistance and etc.) of fully passive arrays (0T1M) various resistive switching memory based structures for the memory cells has been offered in literature such as 1T1M [13, 14], 4M1M , 1S1M [16, 17, 18, 19, 20, 21, 22], 1D1M , and 2T1M . One challenging issue in crossbar array performance is sneak path current which can lead to negative effects on power consumption and limit the array size and other negative effects. Despite of amazing footprint size (4
Other attractive domain for composite memory structure is utilizing them for logic applications by collocating the computing within the memory in the same place. Several number of logic design and implementation research works have recently been proposed using memristor devices. Memristor Ratio Logic (MRL) is a CMOS-Memristor structure approach for combinational logic design . In this method logical values are presented as node voltages, but it is a hybrid approach consisting both memristor and MOS transistors in the crossbar fabric. There are also other methods, such as MAGIC  and IMPLY  in which unlike MRL, memristance of memristors represent logical values. Each approach has positive and negative points regarding required number of memristor or MOS transistors or required time steps.
This chapter discuss 2M1M composite memory array and its application in both memory and logic. The proposed switch provides three modes namely, ON, OFF and No-Change, designed with three memristor. This structure not only can be used as AND, OR, NAND, and NOR logic gates with less computational steps compared to , but also the IMPLY logic can be implemented in crossbar array by this memory cell. The proposed cell is a pure memristor memory cell as 2M1M. The read and write operations are done by the same memristor circuits without need for additional circuitry within memory fabric. Thus, significantly reducing the number of required elements and simplifies the crossbar structure. The technique presented in the reading circuit does not need an isolated access to the memristor node which in turn reduces circuit wiring, and leads to a very simple structure with less complexity. Proposed structure provides an effective gating mechanism by which memory elements can be partially isolated from the access line during reading cycle which considerable reduces the sneak path currents. The remainder of this chapter is organized as follows: Section 2 introduces memristor-based switch circuit and its application and performance in the proposed memory cell. In Section 3 the proposed crossbar structure is discussed. Logic implementation and computational operations by 2M1M memory cell are presented in Section 4 and some explanation about sneak path are discussed.
2. A 2M1M memristor cell and its functionality
2.1 2M1M switch circuit
The 2M1M three state switch  which functions in ON, OFF, and NC are shown in Figure 1. As it can be seen, the proposed memory cell comprises of three memristor devices XA, XB and XC. XA and XB devices are the access devices and they isolate the target device XC which stores the information. There are three terminals A, B, and C in this structure in which A and B are considered as input terminals and Va and Vb (as input voltages of ‘−
When both inputs are ‘0’ (−
For logic 1, according to the fourth row of the Table 1, when both inputs are in the same value of +
Otherwise, if the value of input voltages is different as (+
This state is called a NO-Change state. To have a timing analysis of switches operation, according to :
Because in the fourth combination of the truth table of memristor based switch (Table 1), memristor XA is parallel with memristor XB then
By integrating (8) and also assuming that , is given by
and also by supposing the initial state of memristor XA is
Thus, the required time for change state of memristor XA and XB is given by:
In memristor XC the required time for the change of state is:
Therefore, the total time to change the cell state,
2.1.1 Simulation result for 2M1M switch circuit
This is in general agreement with the simulation results as presented in follow,
Despite several memristor SPICE models which are presented in [28, 29], the simulation results are performed using Biolek model presented in . This model is selected due to the fact that, it can be utilized in mathematical analysis for power and delay estimation besides its validity to characterize the memristor switching behavior. PSPICE software has been utilized to perform the simulations. The simulations are carried out by using the parameters in Table 2, and for a fair comparison, these parameters are similar with  to evaluate functionality of the design.
Different combinations of inputs which are applied to the switch are shown in Figure 2. As it can be seen the simulations results are in agreement with the truth table of Table 1. Here the voltage is applied and output logics is represented by memristance of the XC. Delay or settling times for this switch is defined by the time which XC memristance reaches to its final value. According to the simulation results, this time is 1.11 ns which is also in agreement with theoretical calculations.
2.2 Write and read operations
For the write operation, the memory cell should work based on the first and forth rows of Table 1, respectively for writing ‘0’ and ‘1’, as descried in details in subsection 2.1. For read operation, unlike previous works, these cells do not need any additional wiring or complicated sense circuitry. This is because in this circuit memristor change inertia, as shown in Figure 3, is exploited. In general, the READ operation is done by floating node B and applying READ signal
In read process method, a pulse
which in terms of logic vales can be described as:
With this technique we can increase reading speed and reduce power consumption. In addition, if we read the output value from port A instead of node M, this read method does not require any additional wiring to access node M. This considerably reduces fabrication and wiring complexity of the proposed crossbar structure.
3. 2M1M Memristor crossbar architecture
In crossbar architecture the 2M1M memory cell can be used effectively as shown in Figure 3c. While, there is no need CMOS transistors for each cell within cross bar fabric in this architecture. As it can be seen in Figure 3c, the similar nodes of memory cells in the crossbar structure are connected to each other in the horizontal rows nodes Ai and Bi are of the cells are connected to each other separately while in vertical columns modes Ci are connected to each other. The desired reading or writing operation are performed by applying appropriate voltages in suitable rows and columns to activate a cell and disable others.
3.1 Write operation in the crossbar
For write operation in the crossbar architecture, like a single memory cell, appropriate input values need to be applied to the memory cell based on Table 1. This means that, both applied voltages
As can be seen in the Figure 4, Z2 is the hazardous zone because in this area same voltages as the target cell (−
Resistor equivalent circuit of this zone is depicted in Figure 4b. This floated port connection reduces current through XC memristor of the unselected cells (≈ 0) which keeps the stored values of the cells untouched. The rest of the rows and columns in the cross-bar structure are connected to ground. Thus, points A, B and C of cells that are in zones Z3 and Z4 are either floating or connected to GND. the logical state of these cells therefore do not change during write operation. Although, maybe one of the two memristor XA and XB is sufficient to perform write operations and by help one of them could to done correctly write operation but as mentioned, this structure is designed to be based on a three-state switch ON, OFF and NO Change. The second case is used to high impedance operation for memristors without changing of output memristor in practice reading that through this can reduce the sneak paths current. In addition, one of the applications of these cells has been mentioned is the implementation of logic circuits which is explained in the Section 4. Please note that in this structure cells in the same column are almost independent and can be written or read simultaneously. This makes it possible to have a parallel read/write process on these cells for higher rate memory access operations or combine a number of them forming data “word” rather than collections of single bits.
In the write operation as can be seen in Figure 4a, the memory cells 21 and 23 are in zone 2 and they are the neighboring cells of the target cell for write operation. The equivalent resistor-based circuit of these cells are displayed in Figure 4b. Write operation of the memory cell in 3×3 2M1M crossbar array is simulated in Figure 5a and b. This memory cell is functioning even by having a time difference between the applied voltage input
3.2 Read operation in the crossbar
Regarding read operation, there are four zones in the crossbar as described in previous section. During read operation, as shown in Figure 6a, by applying voltage VR to node C and stored bit in XC can be read as a voltage from node A. Suppose that we want to read from cell 22. The read operation must be performed in 2 stages; in the first stage, memristors XA, XB of the Z2 memory cells are changed to high impedance (
Another consideration which is so important in this crossbar architecture is effect of neighbor cells in the output readout value. In this case the circuit can be assumed as a resistive network and areas involved in this operation are Z1, Z2 that can be seen in Figure 6. Sneak path current is considered as one of the most important issues in memristor crossbar memories. Here, XA and XB of the neighbor cells to “gate” effect of the XC memristance of the neighbors from read signal are used. By changing memristance of XA and XB memristors of the neighbors to
by selecting of
The second voltage
4. Logic implementation and computational operations by 2M1M memory cell
Composite memory cells can be applied to implement digital logics. In addition to its memory application, the proposed memory cell is capable of implementing logic which makes it capable for in-memory computing applications. Here, in this section we are assessing the logic implementation of the proposed architecture with 2M1M cells.
4.1 Logic gates with 2M1M switch
From switching point of view, this circuit is a three state switch as ‘ON’, ‘OFF’ and ‘No-Change’. Interestingly, this switch can also be used as logic gates. By setting the initial memristance value of the output memristor to
The input voltage pulses with amplitude +
The truth table of different 2M1M logic gates has been in presented in Table 4, by showing different input combination voltages, output voltage and resistance state of the output device. Different 2M1M logic cells, their implementations on memristor crossbar array and the simulation results corresponding to each AND, NAND, OR, and NOR logic gates by using 2M1M cells for different input combinations have been displayed in Figure 7. In Table 5, the proposed 2M1M logic gates have been compared in terms of number of with IMPLY logic  and 4M1M . It has been shown that the proposed logic requires only one computational step to implement in-memory logic for AND, NAND, OR, and NOR gates. Also, the number of required devices to implement all of these logic gates are 3 devices included in a 2M1M cell structure.
Sneak path current is considered as one of the important challenges against practical application of memristor crossbars. During reading operation the sneak path currents through neighbor cells can affect readout value of the target cell. To eliminate or reduce the sneak path in the crossbar array several methods have been proposed by researchers. In general, proposed methods can be divided into two categories. In the first approach [33, 34, 35, 36], researchers focus on device level structure of the memristor or read process in the crossbar to make it more resilient against this effect. Among these methods is the way provided in  in which read operation is done by an algorithm in several stages. This method improves the sneak path problem but increases read time and require additional circuit to realize the read algorithm stages. Another approach relies on memristive devices with inherent nonlinear structure such as [34, 35] in which a three-terminal memristor device is proposed to solve this problem. In another approach as presented in  to eliminate sneak path currents separate columns are considered for each element in the crossbar architecture. That increases cell area and therefore reduces the memory density. In the second approach, to solve the problem of sneak path currents, it is suggested to add additional switches to each memory cell in the crossbar architecture to separate reading path of the target cell from the other unwanted paths. There are several suggestions in this approach, but the most popular structure is 1T1M (one transistor for one memristor) . This structure uses a transistor to separate each cell from other cells during read operation. In this way, added transistor is the gating element of the cell. This method has problems due to the scalability considerations of the CMOS-memristor structure . In  diodes, instead of transistors, have been suggested to reduce sneak path. There are difficulties with this approach as well due to diode behavior. In another approach , back-to-back memristors are proposed to overcome the problem of sneak path current in which always one of the memristors is in
In this study, effect of sneak path can be easily reduced using proposed gating mechanism created by XA and XB memristors in the cell. By changing state of these memristors to
With this approach equivalent circuit of the neighboring cells in a row is as shown in Figure 9. Interestingly, target cell (first cell from left) sees an equivalent resistor of the network which is almost independent from stored values (in terms of
By providing the structure and strategies for array-based 1S1R [16, 17, 18, 19, 20, 21, 22], many of the structures have offered while having high density 4
In summary, this chapter discusses the resistive switching based composite memory cells and offers a solution toward the limitations within the current state-of-art 0T1R fully passive arrays and 1T1R active arrays to implement more efficient compute-in-memory structure for future beyond von-Neumann computing architectures. The first section of this chapter briefly review different resistive switching based composite memory arrays and discusses their advantages and limitations toward compute-in-memory applications and implementations. The next section, define a 2M1M memory array cell and analyzes its switching characteristics and the write and read operation principles within the crossbar structure. The final section of the chapter discusses the logic application with 2M1M switch and its capability to implement AND, NAND, OR, and NOR logic gates within 2M1M memory array structure and its compute-in-memory feature. Also, this section discusses the problem of sneakpath within the composite memory arrays and 2M1M array structure. We hope this chapter provide a good basis toward development of resistive switching based composite memory array platforms and providing a good insight over 2M1M structural benefits for compute-in-memory applications.