There is no doubt that scaling down of Si-based complementary metal-oxide-semiconductors has reached its limit on performance with the count of MOS transistors in commercially available CPU crossing 15 billion . Although, a 2020 report  states that according to INTEL, there is enough scope of higher transistor density with every possibility of existence of Moore’s Law, a wide strata of material scientists believe in bringing about improvements through exploration of emerging materials .
Carbon and its allotropes have always garnered sincere attention of researchers across industries and academia. Due to presence of two electrons in the p-orbital of carbon, the bonding structure offers interesting versatility. So far, the electronic application with carbon-based materials is concerned, the sp2 hybridized carbon materials have shown extreme prospect. Both graphene and carbon nanotubes, representing sp2 hybridized form of carbon, have remained at the core of persuasion as alternatives of Si for electronic device applications. However, as graphene does not have any inherent bandgap, semiconducting CNTs find a certain edge over graphene.
The first report of CNT based field -effect transistor (CNT-FET) at Delft University and IBM [4, 5] was based on classic back gate geometry similar to Si-based FET. Within a very short period of time, ultra-high mobility to the tune of 80,000 cm2V−1 s−1  was demonstrated in semiconducting single-walled-carbon-nanotubes (SWNTs). Such high carrier mobility, was further correlated with electric current capacity of CNTs to the order of 109 A cm−2 , thermal conductivity of CNTs (at room temperature) upto 3,500 Wm−1 K−1  and excellent mechanical strength . The entire scientific community was gaining every confidence on CNTs as future substitute of Si. However, it took more than a decade for first CNT based computer to see the daylight [10, 11]. In spite of magnificence of CNTs are electronic materials, there were several bottlenecks that refrained this material from mass scale implementation through standard fabrication facilities. Continuous research efforts, through the entire period since first report of CNT-FETs, have cautiously addressed each challenge. The saga of such efforts is comparable to any epic as right from fabrication, processing hurdles, to implementation of CNTs on substrates, none of the step could be easily achieved and/or optimized.
As a matter of fact, the level of purity that is the requirement benchmark for semiconductor fabrication facilities, is not yet achieved with mass scale yield of semiconducting CNTs, thought to be the key constituent of ‘beyond CMOS’  technology. Basically, the chiral angle of CNTs decide if they are of metallic and semiconductor nature. While metallic CNTs offer low bias ballistic transport , it is the semiconducting CNTs, particularly SWNTs, that are appealing because of intrinsic switching behavior when applied as active layer in FET structures. However, in contrast to metallic nanotubes, their semiconducting counterparts suffer from lower conductivity. Chemical doping can definitely be employed to alleviate this shortcoming; however, it needs consideration that dopant introduction in CNTs distort the sp2 structure and leads to higher scattering and subsequent lowering of carrier mobility . Peng et al.  have applied intrinsic form of CNTs to obtain a high-performance CNT FET employing a doping -free process. The authors were successful in growing high purity parallel arrays of CNTs directly on insulators, a remarkable achievement towards maintaining perfect sp2 lattice of CNT. Synthesis efforts has, thus, came across exceptional spectrum of efforts to control the tube diameter, and improving semiconducting to metallic SWNTs ratio.
Dendritic networks of CNT films have also been employed as active layer in FET structures through solution methods . In such cases, however, FET performance is seriously challenged by bundling induced lowering of mobility . Another aspect of CNTs based electronic devices that warrant critical consideration is the formation of Schottky Barrier (SB) between semiconductor and metal . Performance of devices is seriously challenged under such case as presence of SB severely limits the injection of carriers from metal electrode to semiconductor or vice-versa, a critical problem towards development of electronic devices. Javey et al.  and Zhang et al.  had demonstrated ohmic contacts using semiconducting CNTs using Pd and Sc to the valence band and conductance band of CNT respectively. Back gated FETs developed in such manner had exhibited near to ballistic conduction and barrier independent injection of electrons into conduction band of CNT at temperature down to 4.3 K. Another important milestone in CNT based device fabrication was self- aligned gate structure, an important requisite for large IC fabrication, demonstrated by Zhang et al. . Next, the term ‘complementary’ in CMOS needs consideration, and an ideal CMOS circuit requires symmetric behavior by ‘n’ and ‘p’ devices. However, such condition is not followed by Si and most of the conventional semiconductor materials . The present strata of semiconductor materials offer very high electron mobility if compared to hole mobility. And in this particular aspect, semiconducting CNTs are strikingly, miles ahead. As the conduction and valence band structure in semiconducting CNTs exhibit perfect symmetry near Fermi level, same carrier mobility for both charge carriers could be obtained. Such behavior, supported with perfect ohmic contacts possible with semiconducting CNTs lead to highly symmetric CMOS structure with CNTs . Finally, one has to note two advantageous facets over CMOS fabrication - (i) that CNTs can be implemented in fabrication process without need of doping (as generation of carriers in dependent on contacts), relieving several costly steps of fabrication, and (ii) CNTs have been successfully demonstrated for pass-transistor logic (PTL), where signal has been demonstrated to be applied to any of the three terminals of FET [23, 24], that invariably indicates that paradigm shift in semiconductor industry is not far away.
Still, as published in a recent report , semiconductor fabrication industry is still working on some of the basic bottlenecks that includes – (i) difference in electronic properties of individual nanotubes, (ii) placing of nanotubes in circuits (one has to remember that although single CNT devices have outperformed Si based devices of same size; not only handling a single CNT at mass scale is a critical challenge, such devices are not capable of handling strong electrical signal) (iii) CNTs in bundle lower carrier mobility, (iv) requirement of purity in CNT yield (in the sense that semiconducting CNTs should have higher percentage of yield), (v) inability of exposing CNT deposited chips to plasma etching etc. At this point, Anthony Vicari, a material analyst at Lux Research, in Boston can be aptly quoted – “Historically, carbon nanotubes have shown impressive boosts in the lab that have been difficult to scale to a product” .
It is therefore quite pertinent that consideration of CNTs as future electronic materials, to be more precise, as substitute of Si and its counterparts, has enough scope to be encouraged while a significant spectrum of nooses need to be unfastened. Scientists from both industry and academia have a lot to reveal.
This volume looks forward to introduce readers to a cautious gamut of topics, right from synthesis and purification of CNTs to fault tolerance in CNT Transistors based multi valued logic. Readers will be able to generate ideas through elaborate discussions on CNT composites for electronic applications and illustration of CNTs as future energy storage device. The topics have been chosen so as to cater a material enthusiast at initial phase of research and an avid researcher in this field as well.