Open access peer-reviewed chapter

Band Gap Modulated Tunnel FET

Written By

Brinda Bhowmick and Rupam Goswami

Submitted: November 23rd, 2017 Reviewed: March 1st, 2018 Published: July 18th, 2018

DOI: 10.5772/intechopen.76098

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This chapter presents bandgap-modulated tunnel field effect transistor (TFET) and discusses its simulation and modeling. A geometry of TFET, the heterojunction TFET, is considered, and different electrical parameters are discussed using Technology Computer Aided Design (TCAD) tool. The effect of the heterojunction on the characteristics is observed through the variations in the length and mole fraction of the pocket layer adjacent to the source. An analytical model is further presented for gate-drain underlap TFET using 2-D Poisson equation and Kane’s interband tunneling model. The results are validated with the output from the TCAD tool.


  • heterojunction TFET
  • TCAD
  • analytical model
  • subthreshold swing
  • tunneling

1. Introduction

Tunnel field effect transistor (TFET) is an asymmetrical gated p-i-n device. Unlike thermionic conduction in metal-oxide-semiconductor FETs (MOSFETs), its working principle is based on a band-to-band tunneling (BTBT) mechanism [1, 2]. This amendment results in a reduced subthreshold swing (SS), low off-state leakage currents, and less short-channel effects. Recently, numerous structural and material designs of TFETs have been proposed with an objective to achieve improvement in subthreshold swing (SS) and off current. A few of them are bandgap-engineered TFETs [3], graphene nanoribbon TFETs [4], gate-engineered TFET [5], and strained silicon-germanium TFETs [6]. Double-gate TFET [7], dual-material gate TFET [8], hetero-gate dielectric TFET [9], and heterojunction TFETs [10] have also been investigated for improved electrical parameters of TFET. Generally, TFETs have a very low current as compared to ITRS requirement. In order to get a high ON current, a high-k gate dielectrics are preferred. High-k gate dielectrics causes improved capacitive coupling between the gate and the source-channel tunnel junction, resulting in an increased current in TFET. Moreover, to decline the effective oxide thickness at the tunnel junction, high-k gate oxide is used so that the gate-tunneling current can be reduced. Actually, due to these reasons, the recent trend is to use high-k materials as a better replacement of the conventional SiO2 (silicon dioxide). On the other hand, it causes a significant ambipolar current. The gate-drain underlap structure in association with heterojunction can be adopted to diminish ambipolar current [2]. A silicon-germanium (SiGe) layer is used at the tunnel junction so that bandgap and tunnel width can be modulated. Electrical parameters have been investigated for various Ge-mole fractions.

Technology Computer Aided Design (TCAD) simulation is a complex iterative mathematical process, and hence various analytical models have been proposed in order to develop a better understanding of the physics-based principles of TFETs and obtain results not constrained by computational time [11]. A number of analytical models based on Poisson equation have been proposed in the study for different geometries [12, 13, 14]. In this chapter, a mole fraction-dependent model has been proposed and validated.

This chapter is organized as follows: first, the heterojunction gate-drain underlap tunnel is discussed, and in the second section, the electrical parameters of the heterojunction gate-drain underlap tunnel FET (UL-HTFET) is investigated with the help of TCAD simulation. The third section discusses the physics-based compact model and the validation of the model with simulated results. In the last section, the effect of temperature on the electrical parameters is investigated.


2. Heterojunction gate-drain underlap tunnel FET

A 2-D structure of the proposed UL-HTFET is shown in Figure 1. Here, a p + source and n + drain with an intrinsic channel and a δp + Si1-xGex layer at the source-channel tunnel junction are present. The δp + layer can be replaced by a δn + layer too.

Figure 1.

A 2-D geometry of the device (UL-HTFET).

The effect of germanium mole fraction on the UL-HTFET is investigated. Aluminum with work function (4.1 eV) is considered as the gate material. The proposed device spans across a total length of 100 nm with a length of the channel equal to 20 nm. The δp + Si1-xGex layer extends from the source-channel junction up to 1 nm into the channel under the gate. The various doping concentrations are used such as source, 1021 cm−3; drain, 5 × 1019 cm−3; δp + layer, 1018 cm−3; and intrinsic region, 1016 cm−3. In n-channel, the operation of TFET positive gate and drain voltages is applied with respect to the source. Here, voltage at the source is considered as the reference voltage.

The tunnel FET works on the principle of band-to-band tunneling. Here, SiGe layer is added at the channel near the source-channel junction to enhance the on-current.


3. Simulated results of UL-HTFET

Figure 2 shows the Ids-Vgs characteristics of the Si/Ge heterojunction UL-HTFET at different lengths of Lp. When the HTFET is turned on, it shows very high on-current due to the effective bandgap narrowing at the interface of source-channel junction. The Ids-Vgs curves are mainly dependent on n + −doped pocket length (Lp) as shown in Figure 2; as Lp gets longer, the effective area for tunneling width is extended for HTFET. However, the low off-state current in UL-HTFET (9.205 × 10−20 A/μm) when Lp is less than 2 nm, and this indicates that the ambipolar-tunneling effect at drain channel is suppressed. When Lp is 2 nm, as observed, the tunneling width becomes extremely thin to concede tunneling current at Vgs = −0.5 V. This tunneling current interrupts UL-HTFET device performance at off-state. The low Ioff can be achieved at Lp = 1 and 2 nm, and Ion is greatly higher at Lp = 4 nm in TFET. Therefore, an optimum Lp can be located at 1 nm where high ion is achieved and the leakage is suppressed as shown in Ids-Vgs characteristics.

Figure 2.

Transfer characteristics for varying Lp lengths at Vds = 0.7 V.

In Figure 3, the Id-Vgs characteristics of the UL-HTFET is shown. The mole fraction of SiGe layer is varied. With germanium mole fraction of 0.4, the best Ion/Ioff ratio has been achieved (1012). For Ge-mole fractions below 0.5, the device exhibits a better ratio. As the mole fraction increases beyond 0.5, the properties of the n + layer align more with those of germanium than of silicon. With an increase in mole fraction greater than 0.4, the on-current increases but the increase in off-current is more. This is due to an effective band bending at the source-channel tunnel junction by which the tunnel width can be modulated. For a reduced tunnel width in ON state (Vgs = 1 V), more ON current is achieved. However, at OFF state, the current is due to thermionic emission as the tunnel current is insignificant.

Figure 3.

Id-Vgs characteristics of UL-HTFET with varying Ge-mole fractions.

The energy band diagram is plotted at different mole fractions at ON state (Vds = 0.7 V, Vgs = 1.2 V) shown in Figure 4. It is observed that at 0.8-mole fraction of germanium, the ON current is more. With an increase in Ge-mole fraction, the tunnel width reduces and hence enhanced ON current is achieved. In the inset of Figure 4, the variation of valence band with mole fraction is shown. The conduction band variation is insignificant with mole fraction.

Figure 4.

Energy band diagram at ON state.

In Figure 5, the electric field is shown at different mole fractions. The peak electric field is observed around 20-nm length along the lateral direction. This is the source-channel tunnel junction. A high electric field at this location is due to the presence of a large tunnel barrier. With the increased mole fraction (at x = 1), a highest peak is observed, and hence tunneling probability will increase and be responsible for the increased current in ON state.

Figure 5.

Electric field along the channel length in UL-HTFET.

The ON/OFF current ratio and the subthreshold swing are shown in Figure 6. The best ION/IOFF ratio is achieved for Ge-mole fraction of 0.3. In TFETs, an abrupt Id-Vgs plot is obtained where the subthreshold swing varies with gate voltage. Therefore, two types of SS [15] are defined in TFETs: one is the average SS and the other is known as point SS. The average SS is defined mathematically as


where VT is the threshold voltage and VOFF is the value of gate voltage at which the drain current just begins to take off. IT and IOFF are the drain currents at the respective voltages. Point SS, on the other hand, is the minimum SS at any point on the Id-Vgs plot. The plot of average SS for different Ge-mole fractions is shown in Figure 6. A remarkable average SS (37 mV/dec) is achieved at 0.2 Ge-mole fraction.

Figure 6.

ON and OFF current ratios (ION/ IOFF) and subthreshold swing (SS) versus Ge-mole fraction.


4. Development of analytical model for UL-HTFET

4.1. 2-D Poisson equation-based model

In regions 1–4 of Figure 1, the 2-D Poisson’s equation is considered and the 1-D Poisson’s equation is solved on region 5 due to the absence of gate overlap. The following assumptions have been considered while modeling [12, 13, 14, 15, 16]:

  1. No trap charges are considered.

  2. There are no immobile charges in gate dielectric.

  3. Gate leakage current is zero.

  4. Source-channel and channel-drain depletion regions do not have any kind of mobile charges.

In regions I–IV, the 2-D Poisson’s equation is given as follows:


where the subscript i=1,2,3,4 corresponding to regions 1, 2, 3, or 4.

Ψixy,Ni,and i are the two-dimensional potential, doping concentration, and permittivity of the semiconductor material, respectively, in the respective four regions.

The 2-D potential is approximated as parabolic along the depth of the device. So, the assumption for the 2-D potential is considered as


where C0ix, C1ix, and C2ix are coefficients that are functions of mole fraction.

In each of the four regions, three vertical boundary conditions must be satisfied to confirm the continuity of potential and electric field at the gate insulator–semiconductor interface (y=0) and at the lowermost part of the device (y=ts)


where Ψsix is the surface potential, ox is the permittivity of gate dielectric, tox is the gate dielectric thickness, and vi=VGSVfbi. The gate voltages with respect to source and the flatband voltage are represented by VGS, and Vfbi, respectively. The bandgap EGi is a function of Ge-mole fraction in Si1-xGex expressed as a linear interpolation of the bandgaps of Si ( 1.10 eV) and Ge ( 0.66 eV):


Using the boundary conditions of Eq. (4), we obtain the coefficients of Eq. (3) as follows:


Using the coefficients of Eq. (6) in the polynomial in Eq. (3), the 2-D Poisson’s equation can be expressed as



and ξi=qNiεiki2vi.

Eq. (7) has a solution of the form:


The surface potentials for regions I–IV of the device are represented by Eq. (8). For region V, we apply 1-D Poisson’s equation:


to get


The coefficients A1,B1,A2,B2,A3,B3,A4,B4,C1, and C2 must satisfy the boundary conditions for the continuity of surface potential and electric field in the five regions:


where VDS is the drain voltage with respect to source, and ni1 and ni2 are the intrinsic concentrations of the Si1-xGex layer and silicon, respectively. Here, a, b, c, d, and -f are the various positions along the channel at which the boundary conditions are applied. Their values are mentioned in the inset of Figure 1. The width of the depletion region in the source is expressed as




Using Eqs. (8) and (10), the lateral electric field for the five regions is given as


for i = 1, 2, 3, 4 corresponding to regions I, II, III, or IV.



The vertical electric fields for the different regions are expressed using Eqs. (3) and Eq. (10) as


for i = 1, 2, 3, 4 corresponding to regions I, II, III, or IV.



The drain current is calculated by integrating the band-to-band generation rate GBTBT over the volume of the device




where E=Ex2+Ey2

4.2. Validation of the analytical model

The developed analytical models are validated with simulation data from TCAD. Figure 7 shows the plot of lateral electric field at the surface of the UL-HTFET in the channel region for different Ge-mole fractions of the silicon-germanium layer, at VGS=1.2V and VDS=0.7V. It has been seen that the modeled values match with the simulated values of lateral electric field except that a small mismatch in the field is observed at the position in the channel where the gate-channel overlap terminates.

Figure 7.

Variation of lateral electric field at the surface in the channel for different Ge-mole fractions.

A plot of vertical electric field at the surface of the device versus horizontal position in the channel region is shown in Figure 8 for different values of Ge-mole fractions at a fixed drain voltage of 0.7 V and a gate voltage of 1.2 V. For all the cases, it has been observed that the modeled results closely approach the simulated results. The simulated vertical electric field is slightly different as compared to the modeled ones near the junction of silicon-germanium-silicon in the channel region; however, at other positions in the channel, there is a close match between the modeled and the simulated values of vertical electric field.

Figure 8.

Variation of vertical electric field at the surface in the channel for different Ge-mole fractions.

The variation of drain current with gate voltage has been computed and portrayed in Figure 9. There is a close match between the model and the simulated data.

Figure 9.

ID-Vgs characteristics at Ge-mole fraction equal to 0.5, gate voltage equal to 1.2 V, and drain voltage equal to 0.7 V.


5. Dependence of threshold voltage on temperature

An algorithm for the extraction of threshold voltage in heterojunction TFET is presented in Figure 10 [17]. The algorithm uses the analytical model of Section 4 to plot multiple curves of surface potential versus position for different gate voltages and fixed drain voltage. The advantage of this algorithm is that the procedure is completely computational, and the threshold voltage can be determined without deriving the transfer characteristics. Moreover, the method can be extended to fit different threshold voltage extraction methods by changing the fitting parameter [17].

Figure 10.

Algorithm for the extraction of threshold voltage in heterojunction and homojunction TFETs [17].

The model takes into account the dependence of temperature. The method involves geometrical constructions on a plot of surface potential versus position and using mathematical parameters to define a variable range_point.

A plot of threshold voltage versus temperature is shown in Figure 11. The plot shows that for high-k gate dielectric TFET, the threshold voltage rises with an increase in temperature, whereas for low-k dielectric, the threshold voltage remains almost constant. The simulated values of threshold voltage have been derived using linear extrapolation method of determining threshold voltage. The method involves the construction of a tangent at the point on the transfer characteristics where the transconductance is maximum. The value at which the tangent intersects the gate voltage axis is taken to be the threshold voltage.

Figure 11.

A plot of threshold voltage versus temperature for dielectric constants, 3.9 and 22.


6. Conclusion

This chapter has presented a comprehensive evaluation of a bandgap-modulated UL-HTFET. The simulation analyses have examined the different electrical parameters and their dependence on the pocket length, mole fraction of the SiGe layer, and gate voltage. An impressive on-off current ratio of >1012 and a subthreshold swing less than 60 mV/dec are observed. An analytical model based on 2-D Poisson equation has been developed for the gate-drain underlap heterojunction TFET. The modeled values of surface potential, electric field, and drain current satisfy the results of the simulation. Furthermore, a temperature-dependent algorithm has been discussed to extract threshold voltage in heterojunction TFETs, and a validation has been presented for the plot of threshold voltage at different temperatures.



The authors would like to acknowledge Computational Laboratory, Department of Electronics and Communication Engineering, National Institute of Technology Silchar, India, for supporting the work.


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Written By

Brinda Bhowmick and Rupam Goswami

Submitted: November 23rd, 2017 Reviewed: March 1st, 2018 Published: July 18th, 2018