To save energy on an electric power grid, the idea of redesigned ‘micro-grids’ has been proposed. Implementation of this concept needs power devices that can operate at higher switching speeds and block voltages of up to 20 kV. Out of SiC and GaN wide band gap semiconductors, the former is more suitable for low- as well as high-voltage ranges. SiC exists in different polytypes 3C-, 4H- and 6H-. 4H-SiC due to its wider band gap, 3.26 eV has higher critical electric field of breakdown (Ec) and electron bulk mobility compared to 6H-SiC. Even with all these benefits 4H-SiC full potential has not yet been realized. This is due to high trap densities (Dit) at the interface. In addition to 4H-polytype, in recent years, there is a reignited interest on cubic silicon carbide (3C-SiC), which can be potentially grown heteroepitaxially on 12″ Si substrates, as it would result in a drastic cost reduction of semiconductor devices compared to the successful but exorbitantly expensive SiC hexagonal polytype technology (4H-SiC). In this chapter, we discuss and summarize all different interface passivation techniques or processes that have led to a vast improvement of these (4H- or 3C-SiC/SiO2) interfaces electrically.
- silicon carbide
- interface trap density
- nitrogen plasma
- NO passivation
1.1. Progress in semiconductor devices
The first solid-state amplifier was manufactured by using germanium (Ge) which was seen as the semiconductor material of the future. With time, silicon (Si) turned out to be more appropriate for a plethora of reasons [1–4]. Silica, the source of Si, is commonly available and is easier to get high-purity Si from it. Silicon can easily be doped to produce n-type, p-type and semi-insulating material . In addition to all these, a native oxide SiO2 can be grown on Si using thermal oxidations at relatively low temperatures of around 900°C [6–8]. These properties make Si semiconductor industry favourite. At present, semiconductor industry worth is more than $300 billion . Around 10% of this total is in smart integrated circuits and electronic power devices [10, 11]. In excess to more than 50% of our electricity is conditioned by electronic power devices [12, 13]. These devices are important because they determine the cost and efficiency of an electronic system. Hence, they have a greater influence on the economy of a country. The arrival of devices like the bipolar transistors in the 1950s led to the replacement of vacuum tubes [13, 14], and these improvements made possible the Second Electronic Revolution with Si as the material of choice. Power devices had a vital place in this revolution. In the 1970s, there were bipolar devices with a blocking voltage capacity of 500 V and high current capabilities. Also in 1970, International Rectifier Inc. launched the first metal-oxide-field-effect transistor (MOSFET) . The idea was to switch bipolar devices with MOSFETs for high power use. The MOSFET is a unipolar device and thus can switch at a higher speed. Also, the MOSFET is a voltage-controlled device where the junction transistor is a current-controlled device. Higher switching speed means operation at higher frequencies where other system components such as inductors can be made smaller in size, and voltage control instead of current control means saving of internal energy in the device.
1.2. Need of a wide band-gap semiconductor device
To save energy on an electric power grid, the idea of redesigned ‘micro-grids’ has been proposed [16, 17]. Implementation of this concept needs power devices which can operate at higher switching speeds and block voltages of up to 20 kV . A potential solution for this problem is to use wide band-gap semiconductor (e.g. SiC) power devices . For a power device, the Baliga figure of merit (BFOM)  is given by
1.3. Unipolar devices
Power devices can be divided into two categories—bipolar and unipolar. Schottky diodes and MOSFETs are examples of unipolar devices. In a unipolar device, only one type of carrier (either a majority electron or a majority hole) is responsible for current flow. The device can operate at higher frequencies which results in lower switching losses . There is a flow of both majority and minority carriers in bipolar devices. The slower minority carriers have to be injected and removed to get the device to turn on and off, so in bipolar devices there is power loss due to switching and leakage current. The n-channel Si-MOSFET is a better choice for low voltages (~100 V), and it can operate at high switching speed, 100 kHz. But as the blocking voltage increases, the on-state resistance increases drastically. The SiC-MOSFET enables us to go to higher operating voltages (order of kilo volts) with higher switching speed. This is possible because SiC has a high critical breakdown field, almost seven times that of Si. The specific on resistance (
Bulk electron mobilities are similar for lightly doped Si and SiC (900–1200 cm2/V s). However,
Oxidation of 4H-SiC is a very important processing step during the manufacturing of a device. The performance of a metal-oxide semiconductor (MOS) device is dependent on the quality of the gate oxide layer. Out of many oxidation processes, thermal oxidation is the process most commonly used to form the interface (4H-SiC/SiO2). Thermal oxidation is typically carried out in an oxygen (O2) atmosphere (500 sccm) at 1150°C. The thermal oxidation process has been investigated both experimentally and theoretically by researchers. First-principle calculations done by Di Ventra et al. have shown that during thermal oxidation, atomic oxygen diffused onto the surface of SiC and formed an advancing interface (4H-SiC/SiO2) . Tan et al. confirmed experimentally that the excess carbon atoms diffused out as carbon monoxide (CO) . For thicker oxide layers, their simulations showed that CO may break up either in SiO2 bulk or at the interface (4H-SiC/SiO2). The released oxygen participates in another round of oxidation, and the carbon atoms may lead to the formation of carbon clusters. Di Ventra et al. also proposed the formation of carbon dioxide (CO2) while CO was emitted out through a thick oxide layer. Kanup et al. developed theoretical predictions of the formation of stable carbon pairs and carbon interstitials . These defects combined with silicon interstitials form near-interface traps (
1.5. 4H-SiC/SiO2 interface passivation
Silicon carbide exists in different polytypes 6H-, 4H- and 3C-. A MOSFET fabricated using 6H- polytype has field-effect inversion channel mobility which is much higher than that of 4H- polytype MOSFET (due to higher band gap of 4H-,
1.5.1. Phosphorous interface passivation
In phosphorous (P) passivation, the interface is treated with P source to get a gate oxide with P at the interface. This can be done by using either a gas mixture of POCl3, N2 and O2 or SiP2O7 as a planar solid source to form phosphosilicate glass (PSG), P2O5, under high-temperature (1000°C) annealing in nitrogen environment. With P passivation, we can have different process variations in order to obtain different results, which are discussed in the following sections.
220.127.116.11. Thick PSG process
In thick PSG device, a 70-nm thermal oxide is grown and then passivated by a 3-h P passivation process. During interface passivation, the following reaction takes place, which leads to the formation of phosphosilicate glass. The formation of this PSG layer leads to a high concentration of P at the interface. The P concentration near interface is ~2 × 1021 cm−3 using Secondary Ion Mass Spectroscopy (SIMS), data are not shown.
Bias temperature stress (BTS) test was performed on metal-oxide semiconductor capacitors for a positive/negative bias and results are shown in Figure 3(a) . For a positive BTS test, the electric field is ~+1.5 MV/cm. The value of 0 V for flatband voltage (
Phosphorous process leads to improved interface by making traps electrically inactive and hence leads to higher field-effect mobility in 4H-SiC MOSFETs [6, 30]. Although the values of diffusion coefficients of impurities in SiC are very low, the possibility of P diffusion into SiC cannot be neglected. Phosphorous in the SiC substrate could have two effects: (i) phosphorous in the SiC can passivate carbon di-interstitial clusters and the correlated dangling bonds and (ii) the presence of phosphorous in the substrate can increase the concentration of n-type dopants (P) in the 4H-SiC/SiO2 interface region to produce a counter-doping effect. This phenomenon has been observed in nitrogen-implanted 4H-SiC MOSFET. Both these effects (reduction in interface trap and counter-doping) lead to a lower
18.104.22.168. Etched PSG process
Annealing of an SiO2 layer in a P2O5 ambient converts it into a phosphosilicate glass layer. PSG is a polar material , and if a positive/negative bias is applied at the gate terminal of MOSFET a positive/negative polarization sheet charge is induced at the 4H-SiC/SiO2 interface. The effect of this induced charge is similar to the effect of Na+ ions at the interface. The presence of either charge leads to an unsTable 4H-SiC MOSFET. For example, this polarize charge can change a “normally-off” device to a “normally-on” device. X-ray photoelectron spectroscopy (XPS) results [34, 35] reveal that PSG layers cannot be removed completely by etching in BOE if is grown on 4H-SiC while opposite is true for the layer grown on Si. After BOE etching in the case of SiC, a 2–3-nm Si-C-O-P interfacial layer can still be seen which is equivalent to a phosphorous areal density of 2 × 1014 atoms/cm2 (approximately one-tenth of a monolayer). Before etching, the areal density of phosphorus is 1015 cm−2. We lose P after etching which is reflected in higher trap density for the etched PSG sample, Figure 4. In order to understand this phenomenon, we need to address the following two questions: (i) Is the un-etched PSG layer responsible for the better interface trap and hence high field-effect mobility? and (ii) Is there any difference between the bulk PSG layer and the un-etched layer in terms of induced polarization charge? These two questions are very important in order to understand the field-effect mobility and threshold voltage stability of the devices. An etching experiment on P-passivated MOS capacitors was performed to answer these questions. On etched devices, a thick layer of deposited oxide is used to fabricate MOS capacitors by using a low-pressure chemical vapour deposition (LPCVD) system at a temperature of 650°C. The
22.214.171.124. Thin PSG devices BTS
P passivation of the 4H-SiC/SiO2 interface reduces the
1.5.2. Nitrogen plasma (N-plasma) passivation of the 4H-SiC/SiO2 interface
NO passivation is the process that has been used in the production of commercial SiC MOSFET. This process reduces the
For N-plasma passivation, ground-state atomic N is created in microwave plasma and a portion of these atoms recombine to emit at visible wavelengths. The set-up used to create N-plasma is shown in Figure 9. The snapshot of the spectrum formed during the N-plasma passivation is shown in Figure 10. In the spectrum, a peak is obtained at the wavelength of 589.19 nm. This peak is obtained due to the recombination of active ground-state (4S) N atoms. This recombination is followed by the decay of an excited state in the N2 molecule and gives rise to yellow afterglow . The mechanism, which causes the afterglow, takes place due to the following reaction.
Also, the intensity of yellow afterglow of emission is proportional to the square of concentration of active ground-state atoms. The amount of radiation detected at 589.19 nm is therefore a measure of the atomic nitrogen concentration in the plasma [36, 37]. After N-plasma passivation for the desired time, the recovery step was performed at 1160°C in N2 flow. This step is used to heal the damage caused during the nitrogen plasma exposure of oxide and helps to improve the breakdown characteristics of the devices.
126.96.36.199. Four-hour N-plasma passivation on thermal oxide
Initially, the N-plasma process was used on the interface grown using a standard thermal oxidation. Nitrogen plasma also causes damage to the interface so N-plasma process is followed by a recovery process. Results obtained for a 4-h N-plasma process followed by a 2-h recovery process (from plasma damage) are shown in Figure 11(a) and (b) . The
188.8.131.52. Four-hour N-plasma passivation on deposited oxide
To limit carbon liberation (by minimizing the number of processing steps which causes oxidation) of the SiC, thermal oxide layers can be replaced by deposited oxides. The peak value of field-effect mobility for a companion MOSFET is ~50 cm2/V s (Figure 12), which is significantly higher than “NO-like” device, with threshold voltage again ~4 V (Figure 13). Note that this value is 25% higher than the one obtained with thermally grown oxide [38, 39].
184.108.40.206. Eight-hour N-plasma passivation
The interface trap density after 8-h N-plasma passivation with 6-h recovery is shown in Figure 14(a) for 62-nm thermal oxides [3, 39, 40]. The
1.5.3. High-temperature oxidation
Lately, there has been a growing interest in high-temperature oxidation of 4H-SiC. Studies have shown that if the oxidation conditions are optimized, then the 4H-SiC/SiO2 interface grown after the process has much better electrical properties to the ones grown under standard conditions (1100−1200°C). In the following sections, we see the progress made in this area. Also, we discuss the effect of performing P and N2O post-oxidation annealing on the oxides grown at high temperatures. It has been observed that high-temperature oxidation performed at 1500°C can lead to a better interface with
220.127.116.11. Combined N2O and phosphorous passivations of the 4H-SiC/SiO2 interface with oxide grown at 1400°C
Phosphorous (P) passivation is more effective than N2O passivation in improving the 4H-SiC/SiO2 interface by reducing the number of traps at the 4H-SiC/SiO2 interface. There are some studies performed by Rong Hua et al.  to see the combined effect of high-temperature oxidation with either P or N2O passivation. The MOS capacitor with 1400°C dry oxidation and without any post-oxidation passivation process has the highest
However, the combined N2O- and P-passivation processes have shown a slight decrease in the peak field-effect mobility value (60 cm2/V s) compared to the P-only passivation. This value is still much higher than obtained using N2O passivation (12 cm2/V s). The only drawback for the combined N2O- and P-passivation processes is that the MOSFET still has a negative threshold voltage (
18.104.22.168. Impact of N2O passivation on 4H-SiC/SiO2 interfaces grown at high temperature
The results on high-temperature oxidation (1500°C) have shown a reduction in the interface trap density (
1.5.4. Other interface passivation processes
In addition to all these interface passivation processes, there are some studies done using boron (B) and Sb. Modic et al. have shown that Sb-doped surface channel in combination with nitric oxide post-oxidation annealing can increase the channel field-effect mobility to 100 cm2/V s . Also, Okamoto et al. were able to increase the channel field-effect mobility to 102 cm2/V s by introducing boron atoms to the interface .
1.6. 3C-SiC/SiO2 interface
There is a reignited interest on cubic silicon carbide (3C-SiC), which can be potentially grown heteroepitaxially on 12″ Si substrates, as it would result in a drastic cost reduction of semiconductor devices compared to the successful but prohibitively expensive SiC hexagonal polytype technology (4H-SiC). It has been demonstrated that lateral power transistors in 3C-SiC outperform Si and 4H-SiC devices up to 1200 V, and represent an alternative to gallium nitride (GaN) technology. Also, GaN transistors are normally on, and as a result, it is challenging to control them eclectically. The voltage ratings for which these 3C-SiC devices are targeted for make them useful in automotive and other domestic appliances. Thus, this 3C-SiC technology has a huge potential for reducing the global carbon footprint.
1.6.1. High-temperature dry/thermal oxidation (1200–1400°C) and N2O passivation of the 3C-SiC/SiO2 interface
Due to the smaller band gap of 3C- (2.2 eV) compared to 4H- (3.2 eV), a fewer number of traps lie within the energy band gap of 3C-SiC in a metal-oxide-semiconductor structure resulting in better field-effect mobility . It is found that 3C-SiC has different oxidation chemistry compared with 4H-SiC; 70–80-nm oxide can be grown at 1100°C in 1 h, which is 10 times faster than the oxidation rate of 4H-SiC on the Si face . Also for the Si face in 4H-SiC, it has been observed that mobility increases with decreasing
A 3C-SiC/Si wafer with heterostructure grown on on-axis p-type Si (001) substrate was used in the work. The 3C-SiC epilayer is n-type with a doping concentration of
In conclusion, high-temperature oxidation (1200–1400°C) has been used to grow the 3C-SiC/SiO2. Out of all the oxidation temperatures investigated, 1300°C was found to be the optimum temperature for oxidation. The interface can be improved further by performing the N2O post-oxidation annealing again at 1300°C for 2 h, though this leads to high accumulation of N at the interface. The lateral MOSFET with N2O-annealed oxide yielded a field-effect mobility of 125 cm2/V s, which is twice the value of non-annealed MOSFET, with the gate oxide grown at 1300°C (60 cm2/V s). The low values of σs and larger
I would like to thank all my old colleagues from Auburn University and University of Warwick where all the work had been done. This work was supported by the US Army Research Laboratory, the US National Science Foundation, the II–VI Foundation, and the Engineering and Physical Sciences Research Council. Finally, special thanks to Prof. John R. Williams and Prof. Minseo Park who introduced me to the world of wide band gap semiconductors (SiC and GaN).
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