Some of the fundamental problems of ultra-small MOSFETs beyond sub-10nm channel length are the electrostatic limits, source-to-drain tunnelling, carrier mobility degradation, process variations, and static leakage. The trend toward ultra-short gate length MOSFETs requires a more and more effective control of the channel by the gate leading to new device architecture. It appears that non-classical device architectures can extend the CMOS lifetime and provide solutions to continue scaling. In case of silicon-based CMOS technologies, planar MOSFETs are limited to scaling beyond 15 nm technology node. As simple scaling of silicon CMOS becomes increasingly complex and expensive, there is considerable interest in increasing performance by using strained channels which can improve carrier mobility and drive current in a device. Multi-gate MOSFETs based on the concept of volume inversion are widely recognized as one of the most promising solutions for meeting the ITRS roadmap requirements. A wide variety of multi-gate architectures, including Double-Gate (DG), Gate-All-Around (GAA), Pi-FET and Fin Field-Effect Transistors (FinFETs), rectangular or cylindrical nanowire MOSFETs has been proposed in the literature. In all cases, these structures exhibit a superior control of short channel effects resulting from an exceptional electrostatic coupling between the conduction channel and the surrounding gate electrode. The nanowire (NW) transistors can be seen as the ultimate integration of the innovative nanodevices and is one of the candidates which have gained significant attention from both the device and circuit developers because of its potential for building highly dense and high performance electronic circuits. Recent advances in nanoscale fabrication techniques have shown that semiconductor nanowires may become the candidate for next generation technologies. Si and Ge nanowire transistors are also important because of their compatibility with the CMOS technology.
Nanowires and FinFETs have attracted considerable attention due to their proven robustness against Short-Channel Effects (SCE) and relatively simple fabrication. Silicon nanowire FinFET (SNWFT) is being considered as the candidate for CMOS scaling beyond the 32 nm node due to its high performance, excellent gate control and enhanced carrier transportation properties. Thin and multi-gate controlled body provide FinFETs a superior short-channel effect control, electrostatic shielding from the body bias, relaxing channel doping or pocket implants, commonly needed in planar technologies to avoid threshold voltage (VTH) roll-off . Adequate device VTH is now being achieved by using gate stack engineering. Metal-Gates with High-k (HKMG) dielectric stacks provide the desired VTH by work-function tuning as well as preserving low gate leakage . Various process options are being attempted to affect carrier transport in a different manner. The use of metal gates as replacement for Poly-Si stacks eliminates the Poly-depletion effect, benefiting effective carrier mobility by reducing the transverse field . Additionally, use of undoped channels improves low-field
The most promising among various Si multi-gate MOSFET architectures such as double-gate and tri-gate FinFETs, are nanowire FinFETs due to their superior electrostatic control through gate-all-around structure. Superior gate control, immunity of threshold voltage from substrate bias and excellent carrier transport properties along with more aggressive channel length scaling possibility have made GAA architecture with semiconductor nanowire channel a potential candidate for post-planar transistor design. Two approaches are generally used to fabricate Si NWs as well as other semiconductor NWs: bottom-up and top-down. In the first method, NWs are usually grown using a metallic catalyst on a separate substrate, usually through a Vapor-Liquid-Solid (VLS) growth mechanism. After a chemical or mechanical separation step, the NWs are harvested and transferred to another substrate . In the top down-approach, the NWs are fabricated using a CMOS compatible technology, such as lithography-based patterning and etching . Unlike the bottom-up approach where the NWs are randomly distributed, the top-down method enables accurate positioning of the NWs across the wafer and facilitates the ultra-large-scale-integration (ULSI) for high performance nano-electronic circuits. Moreover, due to processing difficulties related to the length of grown NWs, NW release and gate-etch process, most of the VLS grown NW transistors have omega-shaped gate (Ω-gate) geometry and are thus not full gate-all-around . Among all the promising post-CMOS non-conventional structures, the silicon nanowire transistor has the most unique advantage – it is based on silicon.
In a MOSFET, the carriers encounter various scattering mechanisms on their way towards the drain terminal. Carrier mobility is a well known benchmark to judge the intrinsic performance of a long channel MOSFET. The state-of-the art short channel devices do not operate in the fully ballistic regime (they are at roughly 60% of the ballistic limit) and mobility is related to velocity through effective mass and ballistic ratio. Therefore, understanding the carrier mobility is beneficial to design and engineer new devices for future CMOS generations. The presence of significant resistive and capacitive parasitics as well as lack of large capacitance due to the small size of the NW channel adds complexities to the extraction of the intrinsic NW device characteristics. Simplified assumptions or incomplete device charge simulations generally lead to inaccurate and unreasonable mobility extraction . In the absence of a well-behaved top-down process (as compared to the bottom-up-fabricated NWs with smooth and near ideal sidewalls) results in significant mobility degradation for smaller NW sizes .
Noise is known as a fundamental problem in various fields such as telecommunication, nanoelectronics, and biological systems. The low-frequency noise, or 1/f noise, is the excess noise at low frequencies whose power spectral density (PSD) approximately depends inversely on the frequency and therefore escalates at low frequencies. The 1/f noise originating from the transistors is a major issue in analog circuit design. The 1/f noise is, for example, up converted to undesired phase noise in voltage controlled oscillator (VCO) circuits, which can limit the information capacity of communication systems.
In this chapter we shall present a detailed framework on gate-all-around nanowires and multi-gate FinFETs which will include process and device design and characterization, simulation, and low-frequency noise and tunnelling spectroscopy analyses. Carrier mobility extraction in nanowire and FinFETs using split-CV technique will be described. Channel orientation dependence of the electrical parameters such as current, low-frequency noise will be presented. Self-heating effects in nanowire transistors are also discussed. In Section 2, the growth and fabrication of silicon nanowire transistors and multi-gate FinFET devices will be covered. The detailed fabrication process steps for GAA nanowires as well as tri-gate FinFETs are discussed. 3D device simulation and electrical characterization will also be covered in this Section. Split CV measurement technique is employed for mobility calculation and detailed model equations are formulated for FinFET and nanowire structures. In Section 3, the low-frequency noise characteristics of the nanowire FinFETs will be taken up. Voltage dependence of flicker noise (1/
2. Multi-gate FinFET and Nanowire Transistors
In order to control short channel effects in planar SOI MOSFETs and maintain reasonable electrostatics at a given gate length, LG, a critical Si thickness, tSi on the order of LG/3 is required . Multi-gate devices have been suggested to significantly relax the critical Si dimension in fully depleted SOI (FD-SOI) device architectures and process technology. For this purpose, planar double-gate, vertical double-gate (FinFET), triple-gate (Tri-gate), omega-shaped gate (Ω-gate), penta-gate, inverted T-channel FET, Φ-FET, and GAA nanowires have been proposed by various research groups over the past decade.
While most of these multi-gate technologies have been experimentally shown to benefit from excellent electrostatics and short-channel effects, they commonly suffer from a complicated fabrication process technology compared to planar bulk or SOI technology. Figure 1. shows the device schematic of
GAA NW MOSFETs.
The critical Si dimensions to sustain acceptable electrostatics have been reported . It can be seen that the criterion of Si film thickness may be relaxed for the nanowire MOSFET, which is naturally evolved from double-gate FinFET technology.
2.1. 3D Quantum Simulation of Multi-Gate FinFETs
The simulation of tri-gate FinFET is performed using SILVACO ATLAS3D quantum simulator framework. The Bohm Quantum Potential (BQP) model is included to model the confinement effects in the simulation. Also, calibration of the BQP model against the 2D Schrödinger-Poisson simulation is done for describing the quantum effects in small geometry Si FinFET and nanowire transistors. To model the effects of quantum confinement, ATLAS allows the solution of Schrödinger’s equation along with the fundamental device equations. The solution of Schrödinger’s equation gives a quantized description of the density of states in the presence of quantum-mechanical confining potential variations. When the quantum confinement is in one dimension (along y-axis), the calculation of the quantum electron density relies upon a solution of a 1D Schrödinger equation solved for eigen-state energies Eiv (x) and wave-functions Ψiv (x, y) at each slice perpendicular to x-axis and for each electron valley (or hole band)
is a spatially dependent effective mass in y-direction for the
For the BQP model, there are two advantages over the density gradient method. First, it has better convergence properties in many situations. Secondly, one can calibrate it against results from the Schrödinger-Poisson equation under conditions of negligible current flow. The model introduces a position dependent Quantum Potential, Q, which is added to the Potential Energy of a given carrier type. This quantum potential is derived using the Bohm interpretation of quantum mechanics and takes the following form 
where γ and α are two adjustable parameters, M-1 is the inverse effective mass tensor and n is the electron (or hole) density. The first part of the calibrating the BQP model against the Schrödinger-Poisson (S-P) Model, is to choose a suitable bias for the device. There should be negligible current flow and quantum confinement effects that manifest at the chosen biases. The second part of the calibration is to set the appropriate BQP parameters. The third part of calibration is to choose the quantity to compare with S-P results. The BQP equation is coupled with Poisson’s equation using the charge density terms:
2.2. Tri-gate FinFETs
Typical p-type tri-gate FinFET is fabricated on 1000 Ǻ SOI layer. The FinFET has a fin height of 30 nm. The fin width and fin length are varied from 60-90 nm and 60 nm to 100 μm, respectively. A 50 Ǻ SiO2 gate oxide is grown. Polysilicon gate was deposited of thickness 1500 Ǻ, followed by pocket implantation and a 300 Ǻ SiO2 spacer deposition. A deep source/drain implant is followed. Silicidation is done for contact formation by 300 Ǻ Ni/400 Ǻ TiN depositions with RTA at 550-600°C for 1 minute. A 700 Ǻ - 1 μm thick Al-pad is deposited for contact formation. The final device is annealed in forming gas at 420°C for 30 minutes.
The 3D device structure simulated in ATLAS3D framework  of the tri-gate bulk Si-FinFET with fin height of 30 nm, fin width and fin length of 60 nm and 160 nm, is shown in Fig. 2.The simulation takes into account the quantum effects using the BQP model and the Schrödinger-Poisson solver. The tri-gate structure includes a poly-Si gate and a Si-Fin as a channel on the buried oxide (BOX). A gate oxide thickness of 5 nm is used for device simulation. The energy band diagram is shown in Fig. 3. depicting the conduction and valence band energies as a function of the distance along the Si-fin channel.
Figure 4. shows the measured ID-VGS characteristics of the p-type tri-gate FinFET. Typical device dimensions used for measurements are fin length of 160 nm, and width of 60 nm and oxide thickness of ~5 nm. The device displays excellent performance in terms of near ideal subthreshold slope (SS) (~82 mV/dec), and high Ion/Ioff ratios (~106). Figure 5. compares the measured ID-VDS with the TCAD simulation results which shows an excellent agreement showing the need of quantum 3D device simulation.
2.3. Gate-All-Around Nanowire Transistors
GAA MOSFET is one of the most promising multi-gate structures to extend the scaling of the CMOS devices as it provides the best channel electrostatic control, which improves further with the shrinking of channel thickness. GAA MOSFETs have potential to offer enhanced carrier transport properties compared to planar devices, because of the high carrier mobility on sidewall planes. Careful design and fabrication are critical for GAA MOSFETs for obtaining better transport properties in such structures. The basic nanowire transistor fabrication process flow is illustrated in Fig. 6.
After definition of e-beam lithography (EBL) alignment marks, Si nanowires along <110> direction and S/D pads are defined by hybrid lithography. After reactive-ion etching (RIE) of Si and stripping the resist, nanowires are locally released using a protective photo resist mask and a buffered-oxide etch bath. The suspended nanowires are then RCA cleaned and are subjected to hydrogen anneal process. Although thermally grown oxide benefits from excellent interface with Si nanowires, the facet dependence of the growth usually results in a non-uniform oxide thickness for various crystallographic planes. In addition, thermally grown oxide can induce a significant amount of stress in the nanowires which can alter their intrinsic carrier transport properties . The ALD dielectric benefits from scalability to thinner effective-oxide-thicknesses (EOT) and its excellent conformality ensures that the entire perimeter of the Si nanowire is uniformly gated. The overlapped gate structures are designed for two reasons. First, it helps to minimize the S/D external resistance as the ion-implanted nanowires may exhibit very large series resistance. Second, it is technologically difficult to remove the metal gate stringers under the nanowires if the gate is under lapped. Moreover, any gate-first process to be used after vertical etching of the gate requires an isotropic etch of the gate metal stringers under the nanowires which also laterally etches the bottom gate and results in high extension resistance. After contact via opening and Ti/Al deposition and patterning, the fabrication is completed by a forming gas annealing at 450°C for 30 minutes.
The 3D device simulation is performed in ATLAS3D framework of SILVACO. The simulated device structure is shown in Fig. 7. depicting a cylindrical GAA FinFET structure with fin diameter ~10 nm and fin length of 100 nm wih a surrounding gate oxide thickness of 10 nm. Gate electrode is defined with 70 nm overlap on source/drain. (100) SOI wafer (p-type, 1015 cm-3) was the starting material with 200 nm Si on 150 nm buried oxide (BOX). The gate electrode deposition included 130 nm amorphous silicon (
Figures 8 (a) and (b)show the typical Id-Vds and Id-Vgs characteristics of a GAA n-FinFET, respectively. Typical device dimensions used for measurements are fin length of 100 nm, and diameter of 10 nm and oxide thickness of ~10 nm. The excellent subthreshold performance include a high subthreshold slope (SS) of ~90 mV/dec, and Ion/Ioff ratios ~106.
2.4. Carrier Mobility in FinFETs
Effective mobility extraction for the FinFET devices was based on an improved split C-V method, similar to planar device mobility extraction . This technique relies on the accurate computation of the inversion charge (
for a tri-gate structure and
for a GAA structure;
The transfer characteristics and the gate-to-channel capacitance were measured using the split C–V technique to calculate the effective mobility of devices with fin width (Wfin) being 60 nm and the height of the fins (Hfin) being 30 nm. The effective mobility can be expressed in terms of top, bottom and sidewall mobilities; µtop, µbottom, µsidewall, in tri-gate and GAA structures, respectively, as:
A linear regression can be used to extract the sidewall and top-surface mobility. Eqs. (4) and (5) are used for calculating the effective mobility in the FinFET device from split C-V measurements. The inset of Fig. 9 shows inversion charge density as a function of gate voltage, as obtained from Eq. (5) using split C-V gate-to-channel capacitance. Figure 9 depicts the effective mobility of the FinFET as calculated using Eq. (4) as a function of inversion charge. The extracted mobility values agree well with the results of  for a p-FinFET of with gate length 160 nm.
2.5. Self Heating Effects in Nanowire Transistors
One of the significant challenges in future semiconductor device design is excessive power dissipation and rise in device temperature. With the introduction of new geometrically confined device structures like SOI, FinFETs, nanowires and incorporation of new materials with poor thermal conductivities in the device active region, the device thermal problem is expected to become more challenging in coming years. There is considerable degradation in the ON current due to self-heating effects in silicon nanowire transistors. However, insignificant current degradation is observed in nanowire transistors because of pronounced velocity overshoot effect. Placements of the source and drain contacts also play a significant role on the magnitude of self-heating effect in nanowire transistors. Self-heating and random charge effects simultaneously influence the magnitude of the ON current for both positively and negatively charged single charges. The self-heating affects the ON current in two ways:
by lowering the barrier at the source end of the channel, thus allowing more carriers to go through and
via the screening effect of the Coulomb potential.
There is larger current degradation because of self-heating due to decreased thermal conductivity. Crystallographic direction dependent thermal conductivity is also an important aspect of self heating effects. Larger degradation is observed in the current along the  direction when compared to the  direction.
In SOI devices, the low thermal conductivity of the underlying silicon dioxide layer, which is about two orders of magnitude less than that of silicon inhibits cooling in SOI devices and causes severe self-heating, resulting in a higher channel operating temperature. The temperature rise is significant and depends on the buried oxide thickness, silicon thickness, and channel/metal contact separation. The device mobility is reduced as a result of the elevated temperature and results in reduced maximum drain saturation current. Also, high channel temperature leads to increase in interconnect temperature at the silicon-metal contact and make conduction cooling through the source, drain, and interconnects important. It should also be noted that the thermal conductivity of the silicon films decreases as the film thickness is reduced due to boundary scattering of phonons which further exacerbates self-heating and hence device performance. In brief, as semiconductor technology approaches to two-dimensional and three-dimensional transistor structures and are more isolated from the substrate self-heating effects will become increasingly important.
3. Low-Frequency Noise in Nanowire Transistors
Among various options for multi-gate device architecture, such as double-gate, tri-gate, etc., the nanowire (NW) channel with a wrap-around gate, GAA, has the largest advantage in terms of electrostatic integrity. However, several undesired effects become prominent from the miniaturization of the device dimensions. One such unwanted effect is a strong increase in the low-frequency noise generated in the transistor as the size of the device decreases. With dimension-scaling, it is necessary to also scale the power supplies. Noise cannot be completely eliminated and with small signal strength, the accuracy and measurements are limited in electronic circuits in presence of the dominant noise sources. The low-frequency noise, or 1/
3.1. Low-Frequency Noise Measurement Setup
The standard noise measurement setup included an E5263A 2-channel high speed source monitor unit, a SR 570 low noise amplifier (LNA) and a 35670A dynamic signal analyzer. E5263A 2-channel high speed source monitor unit provided the necessary gate-source and drain-source biases as shown in Fig. 10. The minute fluctuations in the drain-source voltage were amplified to the measurable range using low noise amplifier. The output of the amplifier is fed to 35670A dynamic signal analyzer that performs the fast Fourier transform on the time domain signal to yield the voltage noise power spectral density (SV) in the 1-100 kHz range after correcting for amplifier gain. In order to obtain a stable spectrum, the number of averages was set at 100 and a 90% sampling window overlap was used for optimal real time processing. A computer interface is connected with the measuring system through GPIB connection to control the dynamic signal analyzer and for noise data collection.
3.2. Random Telegraph Signal (RTS)
RTS noise, also known as burst noise or popcorn noise is observed as random switching events in the time domain voltage or current signal. In a MOSFET, if a carrier is trapped in a single trap or localized defect state, the current or voltage signal displays a random shift in the level denoting a change in the channel resistance. The two-level RTS signal signifies only one active trap. However, when multiple traps are involved, the current (or voltage) can switch between two or more states resembling a RTS waveform due to random trapping and de-trapping of carriers and the phenomenon is much more difficult to explain in order to identify the trapping/de-trapping process. For simple two-level RTS pulses with equal height ∆
Mainly two types of traps are identified depending on the nature of trapping mechanism. They are donor and acceptor traps. The donor trap is charged when it emits and electron (i.e. empty) and is neutral when it captures. The acceptor trap is, contrary to the donor trap, charged when it captures an electron and neutral when empty. In MOSFETs, the channel resistance increases with the charged-trap state changing the current (or voltage) to a high state. Clearly, the donor trap causes high current level after emission of carriers, and the acceptor trap causes the high current level when it captures an electron.
Depending on the values of the mean time constants of the RTS, the traps can be characterized of two types. These are the slow traps with high values of time constants, and the fast traps, with the time constants being very small (order of few 0.1 milliseconds). From RTS noise characterizations, interesting information about the trap energy, capture and emission kinetics and spatial location of the traps inside the semiconductor device can be acquired. The multi-level RTS is due to the activation of multiple traps near the quasi-Fermi level. With smaller area devices, only single traps are active as number of traps is less and the RTS becomes a simple two-level signal, with a Lorentzian PSD (1/
3.3. 1/f Noise
3.4. Low-Frequency Noise
Figure 11 shows the RTS of a p-FinFET in time domain in a large span of 60 ms time for
The entire FinFET channel is very thin and close to the interface and thus will be highly sensitive to interface defects. The defect potential perturbation, on the order of several nanometres, will have an effect on a significant cross section of the 10-nm-wide fin, hence producing a large current change when the trap is filled. The relative amplitude Δ
4. Orientation Dependence: Nanowire FinFETs
Theory and measurements on planar transistors show a large difference in mobility for electrons and holes depending on the interface orientation and the direction of current flow in MOSFETs [27, 28, 29]. Figure 14 illustrates the measured drain currents (ID-VDS) for two different channel orientations; (100) and (110). It is observed that the current is higher in (100) orientation compared to the (110) orientation. The change in channel crystallographic direction (and thereby a change in the direction of current flow) greatly influences the carrier mobilities due to direction dependency of the heavy hole eﬀective mass affecting the low ﬁeld hole mobility. The effect of channel orientation is dominant in p-type devices due to different band curvatures along the <100> and <110> channel directions.
The input referred gate voltage noise power spectral density (PSD) of the FinFET is shown in Fig. 15 for two different channel orientations ((100) and (110)) as a function of the gate-source voltage. It is observed that the gate voltage PSDs are comparable in magnitude for both orientations. It is well known that technological factors such as gate oxide quality, gate oxide material, channel material, conduction path, annealing, etc. can be of great importance for the low-frequency noise properties [30, 31, 32, 33]. The gate oxide quality and other technological factors can be considered as unchanged by the channel rotation, which explains why the orientation displays a negligible influence on the low-frequency noise. If the mobility fluctutation noise becomes dominant, the channel orientation may play significant part in determining the noise PSD. This is due to the fact that the carrier mobiliy depends on channel orientation. The difference in noise PSD for the two orientation is large in the subthreshold region. This is due to the fact that the mobility-fluctuation noise generation mechanism is dominant in the subthreshold region, since in the number-fluctuation model, there is no dependence of noise PSD on mobility at a fixed drain-current level. The channel orientation dependence of noise is more dominant in pMOS devices as also reported in reference 34. Stronger current and mobility enhancement in certain orientations may also cause a higher LFN level in the corresponding orientation.
5. Lattice Dynamics: Nanowire FinFETs
Lattice vibrations in small geometry devices and its orientation-dependence are important, which however, have not been studied in detail. Inelastic electron tunneling spectroscopy (IETS) has gained importance for characterization of small-geometry devices and ultra-thin-insulators due to its high resolution and sensitivity and has been used by many previous researchers for studying defects and molecular vibrations in metal-insulator-semiconductor (MIS) structures [35, 36, 37, 38, 39, 40, 41].
The principle of IETS depends on the tunneling current through the ultra-thin dielectric layer of the MIS structures and becomes more sensitive as the tunneling current increases. Tunneling spectroscopy detects interaction of tunneling electrons (through the dielectric) with lattice vibrations of the substrate, dielectric, electrodes or other molecular species as inelastic peaks in the second derivative of the current-voltage characteristics. The application of tunneling spectroscopy was first demonstrated by Hall . The technique of inelastic electron tunneling spectroscopy was properly introduced in 1966 by Jaklevic and Lambe . With high sensitivity and resolution, IETS has been used for various applications including the determination of density of states, molecular vibrations, band gap of superconductors and semiconductors, defects in semiconductors and insulators [38, 39]. IETS has also been used for studying the traps and molecular vibrations in ultra thin oxides  and high-k gate dielectrics . A tunneling spectrum reveals mainly the vibration energies of the molecules between the electrodes and phonon modes. Yanson
The low temperature (77K) inelastic electron tunneling spectroscopy measurement setup includes an E5263A 2-channel high speed source monitor unit for dc biasing, and a SR830 DSP lock-in amplifier for capturing the tunneling spectra by measuring the second derivatives of the current-voltage characteristics. The setup is shown in Fig. 16. AC modulation signal generated from oscillator output of the lock-in amplifier with
The phonon spectra of Si are observed in the 0-70 mV range. Figure 17(a)shows the inelastic peaks in the phonon spectra of Si for FinFET on (100) silicon orientation obtained from the average of six scans after de-convolution of the IETS spectra. The most intense peak is found at 60 mV (wave number 483.9 cm-1). The peak is due to optical phonons at the conduction band minima (X-point) of silicon in transverse optical (TO) mode. Other significant Si-phonons include longitudinal acoustical (LA) phonon peak towards the X point at 47.2 mV (380.6 cm-1), the longitudinal optical (LO) phonon towards X point at 53 mV (427.4 cm-1). The transverse acoustic (TA) mode was observed at 19.7 mV (158.9 cm-1). Phonons of Al-electrodes are observed at 26 and 33 mV. These findings are in well agreement with reported results for Si phonons with (100) orientation . The values of phonon frequencies of unstrained silicon were calculated by Sui et al. using a modified Keating model . The experimental values are compared with these theoretical values. We suspect the minor shifts in peak locations are due to the inherent strain in the small geometry structure of the FinFET. The TO and LO mode towards the Γ point, however, was not observed from the IETS. Figure 17(b)shows similar phonon modes of silicon for (110) orientation. From the Brillouin zone of the Si-crystal the dispersion in (110) direction is calculated along the main symmetry directions Γ→X through K point and X→X through W point . The identified peaks include TO mode at Γ and W points, respectively, at 68 (548.4 cm-1) and 58 mV (467.7 cm-1). LO and LA mode towards X point are found at 54 (435.5 cm-1) and 45.6 mV (367.7 cm-1), and LA towards K point is observed at 41 mV (330.6 cm-1). The TA modes at X and W points are observed at 19.5 (157.3 cm-1) and 26 mV (209.7 cm-1), respectively. The peaks at W point or K point are mostly of weaker intensity compared to the peaks at Γ and X points, which are the conduction band minima for the lattice. Also, unlike the (100) orientation, the symmetry directions in (110) orientation reveal inelastic interactions at the K and W points along with the Γ and X points which describes the Brillouin zone for Si in more detail.
Figures 18 (a) and (b) show the SiO2 phonon modes (in the 129-170 mV range) for (100) and (110) orientations, respectively. The peaks exhibit almost the same energy position for both the Si (110) and Si (100) devices. These peaks include, TO3 mode at 134 mV, LO4 at 144.2 mV, TO4 at 149.8 and 153.4 mV for (100) device. The corresponding peaks for (110) devices are observed at 132, 144.2 148 and 159 mV, respectively. The main discrepancy between the two orientations comes in the magnitude of the phonons. The asymmetric stretch TO4 mode is theoretically found at 148.8 mV  which appears as a strong peak in the Si (110) device, and as a weak peak in the (100) orientation, as also described by . The ratio of intensities of vibration modes may vary for different orientations of the molecular dipoles in the tunnel oxide barrier for different device orientations.
In this chapter, we have discussed silicon nanowire FinFETs in detail. Several important electrical characteristics such as mobility, self-heating, low-frequency noise, impact of channel crystallographic orientation and lattice dynamics are presented for nanowire FinFETs. The fabrication process flow of the nanowire and FinFETs are described. Application of split C-V measurement to calculate effective carrier mobilities is shown and mobility models for FinFETs including side and top-wall mobilities are developed. Low-frequency noise measurements are performed and results of 1/
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