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ICTEAM Institute Université catholique de Louvain, Louvain-La-Neuve, Belgium
ICTEAM Institute Université catholique de Louvain, Louvain-La-Neuve, Belgium
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The development of new integrated high-speed Si receivers is requested for short distance optical data link and emerging optical storage (OS) systems, notably for the Gb/s Ethernet standard  -  and Blue DVD (Blu-Ray, HDDVD) , , . As requirements on bandwidth, gain, power consumption as well as low read-out noise and cost are quite severe, an optimal design strategy of a monolithically integrated solution, i.e. with on-chip photodetector and transimpedance amplifier (TIA), is required.
In optical communication, however, non integrated detectors are usually employed  -  since the particular indirect energy band properties of Silicon make this semiconductor not very efficient for optical reception at 850nm wavelength. As Si is the most widely used and low cost semiconductor material in electronics and due to the availability of low-cost 850nm transmitters, there is yet a great interest and challenge to integrate such receivers. 1 to 10 Gb/s, high sensitivity and low complexity, low-cost silicon photodetectors for the monolithic integration of optical receivers for short distance applications at 850nm are really an issue as the Si absorption thickness required for high-speed (low transit time and low capacitance) favors thin-film technologies for which the responsivity is low. Some solutions exist but at the price of more costly and complex fabrication processes [10-16]. At the system level, owing to its low dark current (pA range) , low capacitor (10fF) for the photodetector  and possibility to integrate this detector with high-performance low-capacitance transistors, global thin-film SOI monolithically integrated photoreceivers have potentially higher gain and lower noise performances which in turn, as we will show here, can increase the IC-sensitivity and alleviate this requirement on the photodetector itself. Furthermore only SOI photodiodes have so far achieved bandwidth compatible with the 10Gb/s specification and even higher data rate among the "easy to integrate" Si photodetectors , ,  and .
In the blue and UV wavelengths, these diodes achieve a high responsivity  and then combine all the advantages of high speed, low dark current and finally high sensitivity . This makes SOI receivers the best candidate for blue DVD applications and future optical storage generation. This also suggests that blue wavelength for multi Gb/s short reach optical communication could be used in a near future under the condition that the recent progresses in blue emitting sources make them available [17, 19].
We present here a top-down design methodology, fully validated by Eldo circuit simulations  and experimental measurements, which allows to predict and optimize, starting from the speed requirements and the technological parameters, the architecture and performances of the receiver. Our approach generalizes the one proposed in  to all inversion regimes. In addition our design strategy is based on the
methodology  and allows one to optimize the diode and the transimpedance in a simultaneous way. Thanks to this modeling and the low capacitance of thin-film integrated SOI photodiodes, we have optimized various monolithic optical front-end suitable for 1 to 10 Gb/s short distance communication or Blue DVD applications that show the potentials of 0.13μm Partially-Depleted (PD) SOI CMOS implementation in terms of gain, sensitivity, power consumption, area and noise.
In section 2 (Optical Receivers Basics), the simple resistor system is first presented as well as its limitations. The transimpedance amplifier is then introduced and its basic theory and concepts such as transimpedance gain, bandwidth and stability are derived. Important parameters to compare transimpedance amplifiers are also discussed as well as architectures most often used in the high speed communication area. Then in section "Design of Multistage Transimpedance Amplifiers", we present our top-down methodology to design transimpedance amplifiers in the case where the voltage gain of the voltage amplifier used in the TIA is independent of the feedback resistor Rf. This is usually the case when the TIA bandwidth is not too close to the transistors frequency limit ft of a given technology and leads to a multi-stage approach. Our design procedure is then applied to the design of a 3 stages 1GHz bandwidth transimpedance amplifier in a 0.13 μm PD-SOI CMOS technology. Finally, in section "Single stage Transimpedance Amplifier Modeling", we present a top-down methodology to design transimpedance amplifiers when the voltage gain depends on Rf. This is the case for very high-speed single-stage transimpedance amplifiers. Our design procedure is then applied to the design of a single stage 10GHz bandwidth transimpedance amplifier in a 0.13 μm PD-SOI CMOS technology and to the design of a 1GHz bandwidth single stage TIA in a 0.5 μm FD-SOI CMOS technology.
The optical receiver is a key element in the optical link. It performs the optical to electrical conversion. The receiver consists of a photodetector followed by a preamplifier and eventually one or more post-amplifiers. The performance of an optical receiver is mainly determined by the preamplifier - photodiode combination. In high-speed communication links, the two most important specifications are speed and sensitivity. In many cases, the speed is fixed by the application, while the sensitivity has to be maximized. The ultimate limitation is noise. The main noise sources are the photodiode and the preamplifier. In a good design, the latter contribution is minimal. Little noise is added when no active components are used in the preamplifier. This is the case for the simplest preamplifier possible presented in fig. 1a: a simple resistor RL that performs both the current - voltage conversion and the preamplification. In this figure, the simple receiver is followed by a buffering amplifier with gain A. Its major drawback is the limited maximal achievable bandwidth when low noise is important. For an input current iph, the output voltage of the simple optical receiver of fig. 1 a) is given by:
in which Cph is the total photodiode capacitance and CinA is the input capacitance of the voltage amplifier. The bandwidth of this simple receiver is thus given by:
The bandwidth is limited by Cph which is often much bigger than CinA and the transimpedance-gain RL of the very first stage. As a result, the required bandwidth constrains the maximal transimpedance-gain RL and accordingly the achievable sensitivity of this receiver. Indeed, the equivalent input noise current spectral density of this front-end is given by :
in which the first term is due to the resistor and the second term to the voltage amplifier. The noise of the latter is concentrated in the equivalent spectral density voltage source at the gate of the input transistor, SvgAmp. As the noise is inversely proportional to RL, low-noise operation implies that the pole is located at a relatively low frequency. This receiver is therefore not suitable for high speed communication applications. To achieve high speed in combination with a large resistor, the latter is used as a feedback resistor with an inverting voltage amplifier. The resulting structure is a transimpedance amplifier.
2.2 The Transimpedance Amplifier
The transimpedance amplifier (TIA) (fig. 1b) is the most widely used preamplifier for high-speed optical receivers. It is based on an inverting voltage amplifier with open-loop gain A and a feedback resistor Rf to convert and amplify the input current iph from a photodiode to an output voltage vout. The transimpedance amplifier is a circuit with shunt-shunt feedback. As a general rule, this reduces both the amplifier input and output impedances by the loop-gain of the amplifier . In turn, this reduction of input impedance allows one for improving the sensitivity and speed trade-off, we faced in the simple resistor amplifier. In this section, various important aspects of transimpedance amplifiers are analyzed.
2.2.1 Bandwidth of the Transimpedance Amplifier
To analyze the TIA frequency behavior, the most important capacitors have been included in fig. 1b. The total input capacitance of the circuit CinT consists of the photodiode capacitance Cph, eventually with its associated parasitics, and the voltage amplifier input capacitance CinA. The output capacitance CoutT is the sum of the amplifier output capacitance CoutA and the input capacitance of the subsequent stage, Cnext. The closed-loop transimpedance-gain is given by:
For a well designed voltage amplifier with sufficiently large gain A and small output impedance Rout this can be simplified to:
This compares well with the simplified transfer function of a system with two well separated real poles p1 and p2, which is given by :
The TIA dominant pole p1 can theoretically be situated either at the input or at the output node. In between those two extreme cases, both poles approach each other and give rise to a complex conjugated pole pair. This intermediate poles placement is best avoided as it results in a bump in the frequency response with overshoot and long settling times of the transients  (see also fig. 2a).
In the case of high speed circuits where the diode capacitance Cph usually dominates the other capacitances and where we try to have the resistance Rf value as high as possible to increase the transimpedance-gain, the dominant pole is usually located at the input node and the transimpedance bandwidth is then given by:
Comparing this bandwidth with that given by the simple resistor amplifier one (eq. 2), we see an improvement by a factor A of the transimpedance-gain-bandwidth product of the transimpedance amplifier. This means that for a given bandwidth, a TIA will have a transimpedance gain increased by A compared to the simple resistor amplifier. To be stable the gain A has however to be constrained, as we will see below.
2.2.2 Stability of the Transimpedance Amplifier
As the transimpedance amplifier contains a feedback loop, its stability has to be assured. To analyze this problem, the shunt-shunt feedback amplifier is presented by its equivalent circuit of fig. 2b . From this figure, the open-loop gain and the feedback factor are easily derived:
The loop gain, which is an important factor in the amplifier stability analysis is given by:
To obtain a stable system, the non-dominant pole of the amplifier loop gain has to be sufficiently higher than the 0 dB crossing frequency, which is given (the dominant pole is assumed at the input node) by:
The latter is equal to the TIA closed-loop bandwidth (Eq. 7). Actually, the equivalence of these two equations demonstrates that a TIA behaves as a voltage amplifier in unity-gain feedback configuration. The stability analysis of both structures is therefore identical . To achieve a reasonable phase-margin, non-dominant poles have to be sufficiently higher than the receiver bandwidth. This implies for the second pole in this structure :
where XA is a factor ranging from 2 to 3 depending on the required phase margin . In general, some extra poles may be present on the internal nodes of the voltage amplifier. These must obviously also be considered during the design and be placed at sufficiently high frequencies to guarantee stability. These requirements ultimately limit the maximal achievable transimpedance-gain and bandwidth.
To summarize, the transimpedance amplifier allows one, owing to its feedback mechanism, to increase the frequency of the dominant pole to a value that is A times higher that the one we would have with a simple resistor. However, by increasing the gain A, the dominant pole approaches the second pole. In order to avoid stability problems, we have to limit the gain A such that the dominant pole stays around 3 times smaller that the second pole (the factor 3 corresponds to the classical 60 phase margin condition in open loop configuration).
2.3 Comparison of Transimpedance Amplifiers
In analogy with the gain-bandwidth product used for an amplifier, the transimpedance-gain (Rf) - bandwidth (BWtrans) product or ZBW has been proposed as the parameter that measures both the speed and the sensitivity performance of the transimpedance amplifier :
In a given device, ZBW is a constant. This tells us that, to some extent, transimpedance gain can simply be traded for bandwidth and vice-versa by tuning the feedback resistor. This substitution is only limited by stability considerations. The maximal achievable bandwidth has to be a factor smaller than the first non-dominant pole of the receiver to maintain sufficient phase-margin. This factor of merit also emphasizes the need in critical high speed applications for photodiodes integrated on chip along with the receivers which can reduce the photodiode capacitance drastically (by a factor up to ten times) by removing the bonding capacitor. SOI has here an advantage over other Si integrated technologies for high speed applications (e.g. 10 GBps) because both the photodiode and the amplifier will have smaller capacitances, and also because SOI photodiodes themselves can achieve such high transit time frequencies .
2.4 Architecture of Transimpedance Amplifiers
Transimpedance amplifier may differ by the kind of voltage amplifiers they use. In the high-speed communications field, two amplifier architectures are mostly used: the single transistor voltage amplifier (STVA) and the CMOS inverter used as an amplifier. A three stages TIA version of both cases is shown in fig. 3a and b. The inverter case has the advantage of auto biasing (the current depends on the gate voltage and the size of the P and NMOS transistor) and then requires no additional bias circuit. The inverter based amplifier has, however, less design flexibility as the gate voltages of the PMOS and NMOS transistors are equal, on the contrary to the case of the SVTA circuit. In very high speed applications, in order to improve crosstalk immunity, differential versions of the transimpedances are also employed and then differential pairs or two single inverters with a dummy branch can be used ,  and .
One can distinguish different type of TIAs by their number of stages. Typical designs use either a single-stage or multi-stage approach. It can be shown  and will be further developed that applications requesting a high bandwidth compared to the technology's ft are limited to single-stage amplifiers as there is no room for placing the extra poles that are inevitably introduced by the multiple-stage designs. However, for frequencies at least 20 to 30 times lower than ft, a multi-stage design is the way to go.
3.1 Optimizing the number of stages of STVA transimpedance amplifiers
We will now describe our methodology to optimize the stages number N that maximizes the voltage gain in transimpedance amplifiers based on N identical STVA amplifiers. It is based on the
methodology and generalizes to all regimes of inversion the methodology of Ingels  that was developed for strong inversion (when we can assume that
). Extension to the CMOS Inverter or the differential pair TIA is quite straightforward. The gain of a single SVTA stage is given by:
where Vea is the Early voltage by μm of length and Leq is an equivalent length in μm. In the case of the amplifier of figure 3a, we have:
The whole gain of the amplifier is then:
For the single stage amplifier, with the dominant pole at the input and only one non-dominant pole at the output, the condition of stability was given by eq. 11. In the case of a multi-stages amplifier, we now have a multiple pole roll-off. To achieve same phase margin with a N pole roll-off than with a single pole, we must now place each of these N poles at a frequency XN.XA higher than the dominant pole frequency. XN is given by :
As XA has to be larger than 2 to 3, XN is approximately equal to N while:
As a result, the ith stage bandwidth of the N-stages voltage amplifier used in a TIA has to be at least (the drain capacitance of transistor M2, Cd2 has been neglected here. This will be addressed latter):
By multiplying both sides of this equation by the gain of 1 stage, ANsi, and isolating the gain on the right side, we obtain that to be stable the gain of 1 stage has to be lower than:
GBWNsi is the gain-bandwidth product of an individual stage i:
where the parameter ft in function of the normalized drain current, idn, or of the parameter gm/Id, is a technological curve for a given length which tends towards a maximum in strong inversion. XC is also a technological curve which depends on the transistor inversion degree and is minimum in strong inversion. We can then rewrite GBWNsi and the stability condition on the maximum value of the gain as a function of a technological curve vs. the inversion degree of the transistor:
This last equation combined with the equation of the gain ANsi (eq. 13) allows us to write the following condition on
for a given BWtrans, a given N, and a given XA:
This implicit equation of
can be solved recursively. We start with a minimum value of
, imposed when the gate to source voltage is at is maximum value, i.e. Vdd, compute fNstab for this
and then compare the two values. If
is lower than fNstab, we then increase
, compute a new fNstab and compare and iterate while
stays lower than fNstab or while
is lower than the maximum
available in the technology. In this last case the gain will not be limited by the stability but by the feasibility.
The method is illustrated graphically in fig. 4. As the fNstab vs.
curves are shifted down by increasing N, the optimal value of
, related to the maximum voltage gain decreases with the number of stages. The gain of each single stage is then decreased (eq. 13), while the overall gain can still increase as we add more stages (eq. 15). We see that in term of voltage gain, an optimal value of stages Nopt exists. In fig. 4a, we can see that for a bandwidth of 1GHz in a typical 0.13μm PD-SOI technology, eq. 25 features a solution in terms of
for N greater than 1 owing to the sufficient value of the ratio ft over fttrans (This ratio is not constant over the
range but is around 130 for its maximum value (ftmax/fttrans)). Therefore, the curve of
vs. N can be calculated (fig. 5 (a)). The total voltage gain, ANs, vs. N and the optimal number of stages, Nopt, can be deduced from there (fig. 5 (b)). In the case of fig. 5 (b), Nopt is equal to 9. In the case of fig. 4b, if we increase the transimpedance bandwidth specification to 10 GHz and then work at ftmax/fttrans ratio of about 10, eq. 25 has no solution for N greater than 1 and Nopt is then equal to 1 (To have stable solutions for N greater than 1 would require in fact to have
lower than its minimum value).
3.2 Current mirror impact on optimal stages number and gain
We have neglected so far the current mirror drain capacitance, Cd2, in the calculation of the output pole as it gave us useful indications on the maximal gain vs. the number of stages for a given transimpedance bandwidth without having to choose neither W1 nor W2. However, Cd2 can lead to significant and unacceptable loss in phase margin. As the drain currents of M1 and M2 are the same, we can relate W2 to W1 by:
and then introduce a factor XC2 independent of W1 and W2 to add to Xc:
As L1 and L2 are usually kept to their minimum value in order to minimize capacitances and area and to maximize speed performances, the maximum value of
has now a dependency on
due to the term XC2:
The selection of
results in a trade-off between dynamic range and other performances. To keep W2 small compared to W1, and then keep negligible the effect of the degradation of XC2 on
, and thus on the gain and on Rf, we see that we need idn2 to be large compared to idn1. This implies to have
and bias the mirror in strong inversion. However, this reduces the dynamic range by increasing the saturation voltage of the mirror Vdssat2. In strong inversion, the latter can be approximated by:
has been chosen, we can deduce
and the maximum number of stages from the maximum voltage gain as done earlier. As can be seen on fig. 6, the optimal number of stages for the gain is now reduced from 9 to 3 when taking into account the correction due to the capacitance of the mirror. Indeed,
now decreases more rapidly with N as, for a fixed
, XC2 increases with N due to the decrease of the ratio idn1/idn2 with
. This indicates that the mirror has a more detrimental effect when increasing the number of stages, which can be observed when comparing the values of vs. N on fig. 6c) and fig. 5b). These values are nearly identical until N=3. This indicates that, as long as its size is kept small because of a good
ratio, the mirror has a relatively small influence while for N greater than 3, the capacitance of the mirror dominates the output capacitance and totally degrades the performances. Once the number of stages has been chosen, we still have to choose W1. This can be done by optimizing noise, area and power consumption.
To analyze the TIA noise performance, we have to consider its major noise sources which are the feedback resistor, Rf, thermal noise, modeled by the voltage noise source,
and the voltage amplifier noise. The latter is concentrated in the voltage noise source at the gate of the input transistor of the amplifier (gate of M1 of the first stage),
. The power spectral density of the feedback noise source is given by:
For the amplifier power spectral density referred to its input, in a first approximation, we can only take into account the noise of the first stage, as, from stage to stage, the relative importance of the noise of each subsequent stage is approximatively divided by the gain of each preceding stage.
is then given by:
are the power spectral densities of the equivalent voltage noise sources at the gate of first stage transistors M1 and M2 respectively. A factor 2 was introduced for
terms, as we assumed that M2 was biased by an identical mirror transistor. In transimpedance design where the TIA bandwidth is usually high compared to the corner frequency, i.e. the frequency at which the 1/f noise of the transistors becomes negligible in comparison with the thermal noise, we can neglect the 1/f terms in
where the parameter has the well known 2/3 value in strong inversion and 1/2 in weak inversion . We then derive:
The total TIA output noise power spectral density is finally given by:
To compare with the noise of the simple resistor system (eq. 3), we can calculate the equivalent input referred current noise power spectral density of the transimpedance amplifier:
As Rf is A (the voltage gain) times higher than RL for same bandwidth and same input capacitance, the TIA noise power is reduced by about a factor A. The shape of
vs. f is plotted in fig. 7a. At low frequencies, the noise is usually dominated by the resistor noise (
However, at medium frequency in the bandwidth of the transimpedance, the amplifier contribution to the noise
exhibits a zero at the frequency
which raises it to a maximum plateau value where
is increased by a factor
compared to its low frequency value in the frequency range between the TIA and amplifier bandwidth. The RMS value of the output noise is given by:
To simplify the calculations, as was done in , the complete integral is approximated by the sum of three components. They are, respectively:
the integral of the noise of the feedback resistor, which we can approximate by:
the integral of the noise of the amplifier up to the transimpedance amplifier bandwidth, which can be approximated by:
This can be rewritten as:
the integral of the amplifier noise from the transimpedance amplifier bandwidth up to infinity, which we can approximated by:
Finally, the TIA RMS value of the output noise is given by:
dependency of the noise is usual and conform to the theory of system in feedback loop. To reduce the amplifier contribution (famp) to the output noise, we see that we need a value of gmeq (and then of gm1) as well as a value of Rf as high as possible. The RMS value of the equivalent input noise current reduces with Rf and is given by:
It can be easily verify that for same bandwidth and same input capacitance, the input noise current reduces by about a factor
. This confirms that the input noise power of the transimpedance amplifier is reduced by about a factor ANs compared to the simple resistor system. Additional noise sources arise from the photodiode dark current Idark, the dark current shot noise, inin,dark and the photocurrent shot noise itself inin,ph. The latter is inherent to the mechanism of photodetection and set the ultimate detection threshold of the ideal detector. We have:
Idark can be calculated from  and is, for a typical SOI diode with a total length and width of 50m, smaller than 10-12A. From eq. 50), this yields a dark current shot noise of around 10-11 A for a transition frequency of 1GHz. Both are usually negligible when compared to the other sources of noise. The total input noise is given by:
As illustrated in fig. 7b, the transimpedance readout noise usually dominates at low input current, while at high input current it is the photocurrent shot noise that dominates.
3.4 BER, sensitivity and dynamic range
In order to achieve a given BER (Bit Error Rate), iph must be at least a factor Q times larger than the RMS value of the input noise. For a typical BER of 10-12, Q must be equal to 7.
By definition, the sensitivity, S, is equal to the minimum input power to achieve a given BER. Since iph=R.Pin, the sensitivity is given by:
where R is the responsivity of the photodiode. It can be calculated with the model developed in . To ensure that the receiver can achieve the required BER, we must have:
where Pinmax is the maximum input power before saturation of the receiver (due to its dynamic range limitation). In the dark, the current flowing through Rf is negligible and the output voltage is about equal to the gate voltage of M1. When a photocurrent iph crosses Rf, the maximum reachable output voltage is Vdd, the supply voltage, minus the saturation voltage of the transistor M2, Vdsat2. We can derive the maximum photocurrent and from there the maximum input power before saturation of the receiver:
3.5. Power consumption
The power consumption of the TIA is equal to the power consumption of the N stages plus the power consumption of the biasing branch:
For a given W1, the power consumption increases with N due to the increased number of stages but also due to the increase of power consumption per stage related to the decrease of
and the related increase of idn1 with N for for a given transition frequency. Once N and the related
have been chosen, the power consumption linearly increases with W1.
3.6 Diode capacitance Optimization
The diode capacitance Cph must be accounted for when optimizing the detector. As discussed in , Cph is proportional to the diode area, Ad, which is fixed by the diameter D of the optical fiber that carries the light signal, and inversely proportional to the length Li of the intrinsic zone. To decrease this capacitance, we could increase Li. However this increases the transit time of the carriers in the diode and thus decreases its cut-off frequency fctr . We will then fix the value of Li such that fctr> fttrans where fttrans is the desired cut-off frequency of the receiver. Note that as fctr depends on the bias of the diode , which is equal to the gate voltage of the input transistor, M1, of the amplifier, Li and Cph depend on
. The choice of Li fixes the capacitance Cph and the number of finger, m, of the diode, and influences Cin. As the amplifier gain is chosen to fulfill the stability requirements, the value of Rf is then adapted in order to maintain the RC frequency of the dominant pole.
3.7 Design of a 1GHz, 3 stages SVTA Transimpedance Amplifier in 0.13 μm PD-SOI CMOS technology
We will now apply the design methodology presented above to the design of a 1GHz, 3-stages SVTA transimpedance amplifier in a typical 0.13 μm PD-SOI CMOS technology. The model has been implemented using Matlab. We assume that the photodiode has a total length and width of 50m, which is typical. We first have to choose a value for
based on Matlab results of fig. 8. As explained above, by increasing
, the ratio of
increases, and XC2 increases compared to XC. As a result, the maximum value of
that we can choose to ensure stability also decreases. While the ratio of
remains sufficiently small with regard to 1, the output voltage swing can be increased significantly by increasing
, while the other performances are only slightly degraded. This can be useful to ensure proper dynamic range margin and reliability against statistical variations on Vth. However, the ratio of
has a very sharp transition around 3.1 and all the performances, even the dynamic range (as
collapses), are greatly degraded after this transition. The mirror suddenly becomes too big compared to M1. A
of 2-2.5 seems to achieve a reasonable trade-off.
Once we have chosen the value of
, the value of
is determined by eq. (28). We still have to determine the value of W1 based on model results of fig. 9. If we increase W1, the bias current increases as
and then idn1 are constant. As the bias current increases and
and then idn2 are constant, W2 also increases with W1. Since W1 and W2 are increased, the input capacitance is increased and then Rf must decrease accordingly, in order to keep the transition frequency at the required value of 1GHz. Note that while the output capacitance is also increased by the increase of W1 and W2, the output pole stays at the same frequency as the output impedance is automatically reduced accordingly by the increase of the bias current. The stability requirement (eq. 18) is thus satisfied. Larger transistors are intrinsically less noisy as gm is increased (see eq. 32). As a result, the TIA noise is reduced when W1 and W2 are increased. This leads to a better receptor sensitivity. A W1 of 4 μm seems to be a good trade-off. Note that the output dynamic range is constant with W1 as it is only a function of
. Thus the input dynamic range and the maximum input power increase with W1 because Rf is decreased. However, in any case, S is well below Pinmax and the required sensitivity is then achieved. A very good sensitivity of approximately 1W is achieved at a wavelength of 405 nm. This demonstrates the potential of SOI thin-film photodiodes for blue DVD and short-distance optical applications. The bias current is about 200A which leads to a power consumption of:
Modeled performances are in table 1. Numerical simulations of the designed circuit have then be carried out using Eldo and a BSIMSOI model fitted for ST transistors. Both values of transimpedance gain given by Matlab and by Eldo are very close from each other and around 330 k (fig. 10a). However, the BSIMSOI model used in Eldo is slightly different from that we have used in the Matlab design. In the latter, we have indeed used technological curves (ft,
transistor capacitances, transconductance, output conductances...) vs. which were extracted from ST transistors measurements done at UCL. The main differences are slightly higher drain capacitances and higher Early voltages for the BSIMSOI model. The slightly higher drain capacitance lowers the frequency of the non-dominant poles. It also decreases the frequency of the dominant pole, but in this case this effect was more than balanced by the increase of Vea,
which results in an increase in ANs and in the TIA bandwidth up to 2.5GHz. This reduces the phase margin of the TIA compared to Matlab and leads to a peaking of around 2.5dB in the transfer function given by Eldo. In order to increase the phase margin and reduce the peaking, we can increase the value of Rf in the Eldo simulation. By increasing Rf up to 700k, the peaking is reduced to a value below 0.1dB, the TIA bandwidth reduces to 1.2 GHz, while the TIA transimpedance gain is increased by 2.1.
We then performed transient simulation of the transimpedance circuit (fig. 10b) for both Rf values. The variation of the output voltage, vout to the 1ns width photocurrent pulses confirms that in a simulation point of view, both circuits (identical amplifier, but different Rf values) are suitable for 1 GBps applications. Compared to the circuit with Rf=700k , that with Rf=332.8k has steeper response (as its bandwidth is higher) but higher overshooting that requires a longer time to vanish (as its phase margin is lower). The multistage amplifier voltage gain ANs that fixes the TIA bandwidth and phase margin, hence its stability, depends on
. This Early voltage is difficult to model carefully, especially in deep sub-micron process, as it can quite vary statistically with fabrication process and short channel effects. It is therefore a critical issue in the design of multistage amplifier TIA. In order to handle it, a sufficient phase margin has to be taken into account. In our case, the phase margin seems sufficient despite the increase of Vea by about a factor 2. The possibility to tune the feedback resistor in the design is another very interesting and efficient solution. This can be achieved by using a transistor to implement Rf and by tuning its gate voltage.
Noise simulations were also performed with Eldo. Eldo spectral power density of output noise voltage are close to Matlab results (fig. 10c). Below 200kHz, both Matlab and Eldo total power densities are identical and are dominated by the feedback resistance contribution. Above, the high frequency peak values are related to the low voltage amplifier power densities multiplied by the voltage gain of the amplifier. The higher peak in Eldo is then explained by the higher voltage gain compared to Matlab. The equivalent RMS value of the input integrated noise given by Eldo is 41.5nA for Rf=332.8k . This is a little higher than the 27.5nA predicted with Matlab due to the peak. For the Eldo simulations with Rf=700k , this noise reduces to 19.1nA. As can be expected, by increasing Rf, the input noise and sensitivity performance of the receiver are improved.
3.8 Design methodology Summary
To summarize, in our multistage top-down design methodology, we first determine the optimal number of stages (which is greater than 1 when the TIA bandwidth is not too close to the transistors frequency limit ft of a given technology) to optimize the voltage gain of the amplifier and hence Rf and the transimpedance gain. This maximum voltage gain was shown to be limited by stability considerations and to impose a value on
. The choice of
results from a trade-off between dynamic range and other performances, while W1 is chosen to compromise power consumption vs. noise and sensitivity.
In this section we will focus on the design of a high-speed transimpedance receiver. The term "high-speed" is in fact here related to technology and means that we have to design at a ratio (ftmax/fttrans)) close to ten or less. In a 0.13μm SOI CMOS technology as used here, it corresponds to 10GBps application. As just discussed in the section 3.1, for this kind of applications, the optimal number of stages is 1. This is simply due to the fact that there is no room to place extra poles in the feedback loop to achieve stability. In fig. 4b, we can also see that the
that we will choose to maximize the gain is low. Combined with the small lengths of the transistors, this will lead to very low achievable voltage gains. If we optimize the design for low voltage gain and high bandwidth, the value of the feedback resistor, Rf, will be low and comparable with the value of the output impedance of the amplifier. In this case the voltage gain will become dependent on Rf. A typical solution to this problem is to use an output buffer. In our case, however, this has to be rejected as it would add an extra pole in the feedback loop. We thus have to accordingly adapt our design scheme to take into account the voltage gain dependency on Rf. In the text, we will call this new case of figure the degenerated case compared to the previous one that we will refer as the non-degenerated case.
4.1 Design Methodology of single-stage Transimpedance Amplifier
The schematic view of the single stage transimpedance is presented in fig. 11a. As previously, to simplify the analysis of this shunt-shunt feedback circuit, we can rewrite its small signal schematic in its canonical form  (fig. 11b). The amplifier is presented as a controlled current source with an output impedance to take account of Rf in the expression of the voltage gain Ao (fig. 11b). The input capacitance, Cin, consists of the amplifier input capacitance, Cg1, and the photodiode capacitance, Cph. The transimpedance gain in closed loop, Zcl is then:
As previously, assuming that the dominant pole is that of the input, the bandwidth of the transimpedance is given by:
Dynamic range (eq. 54) and power consumption expressions (eq. 55) are not changed compared to the non-degenerated case, while voltage gain Ao and non dominant output pole, which is also the bandwidth of the amplifier, BW1s now depend on Rf or its inverse gf:
By making these substitutions, however, noise analysis stays essentially the same. The total output noise power spectral density of the transimpedance (eq. 34), is now given by:
are still given by eq. (30) and eq. (33). The RMS value of the noise is still obtained by integration of
(eq. 38). Again the integral can be approximated by the sum of three fragments (see eq. 41, 42, 47 and eq. 48) from which, only the expression of the amplifier high frequency noise has to be modified accordingly. Eq. (47) now becomes:
Even though the gain and the non-dominant pole now both depend on the value of Rf, the dependence of one compensating the other, the condition of stability can be rewritten as a condition on a maximum gain Aomaxstab exactly as in the non-degenerated case:
Again, we see that, for a given bandwidth and a given phase margin, i.e. for a given XA, the maximal achievable amplifier gain dictated by stability conditions is imposed by technology and inversion degree but is independent of Rf. It is this gain, which is maximum near strong inversion (ft is decreasing, XC is increasing and XC2 is decreasing with
) (figure 11c), that we would like to choose in order to optimize the performances of the circuit. However, as the gain depends on Rf, we cannot directly specify a value of
as it was done in eq. (28) for the non-degenerated case. Moreover, nothing now guarantees that this maximum gain is achievable. Indeed, the gain given by eq. (59) can be rewritten:
where gf is unknown and linked to the gain by eq. (58). As we will now see, for a fixed gain Aospec, one can derive the input transistor width, W1, from its length, L1, its
and specification on the bandwidth. From these considerations we can derive the maximum gain achievable against
. Indeed, fixing Ao equal to Aospec, we find by eq. (58) a condition on the RfCin product to satisfy the temporal specification:
By injecting this equation in the expression of the gain eq. (63), we find:
We can write:
where Cg1o is equal to the input capacitor of the amplifier, Cg1, divided by W1 and L1 and is related to
. In order to keep W1 positive and finite, we need that the denominator of this expression stay strictly positive. This gives the maximum achievable gain, which is an increasing function of
(see fig. 11c):
Finally, we choose to satisfy the constraints and to optimize the performances of the circuit:
where kc is a proportionality factor strictly smaller than 1 according to eq. (67). fig. 11c shows the evolution of the gain in function of the
for kc=0.75. The maximum reachable gain will then be close to the intersection of the two gain characteristics.
4.2 Design of a 10GHz single stage TIA in a 0.13μm PD-SOI CMOS technology
We now apply the design methodology presented in subsection 4.1 to the design of a 10GHz, single stage SVTA transimpedance amplifier in a typical 0.13μm PD-SOI CMOS technology. The model has been implemented using Matlab. Again we used a typical photodiode with a total length and width of 50m. We first have to choose a value for
based on Matlab results of fig. 12. As explained above, by increasing
, the ratio of
increases as well as the ratio of the drain capacitance of M2 to the gate to source capacitance of M1, XC2, compared to XC (the
ratio) for a given
. Then the maximum value of Aomaxstab that we can choose to ensure stability also decreases. As a result, Aospec decreases. As we are working at the technology frequency limit, the stability limitations prevail over the feasibility (which is by the way independent on
). This reduction of Aospec induces a reduction of W1 (see eq. 66) and then of Id1 and Cin. The reduction of Cin is however not sufficient to compensate the decrease of the value of Rf due to the reduction of Aospec (eq. 64). Noise and then sensitivity performances are also degraded when increasing
. The noise in the mirror then increases (see eq. 33). However, in order to have acceptable dynamic range, a
larger than 2 V-1 is required. Increasing
is also beneficial for power consumption. Finally a
of 2.5 V-1 seems to be a good trade-off in between all these considerations for a
of 5 V-1.
However, we also have to determine the value of
. This can be done using model results of fig. 13. Again, the maximum gain is mainly dominated by Aomaxstab. The curve is a non-monotonic one as ft and XC2 (as the ratio of W2/W1) mainly decrease, while XC decreases with
. The curve presents then a flat maximum between
=4.5 to 6.5 V-1, which corresponds to a minimum in W1 and a maximum in Rf (eq. 58). The current Id1 strongly decreases with
up to these values as both idn1 and W1 decrease. When further increasing
, Id1 keeps decreasing but more slowly, as idn1 still decreases but W1 now increases. The input noise also presents a minimum value of around 1.5A that is mainly related to the maximum value of Rf and, then, a minimum in sensitivity in the range of
of 4 to 5 V-1.
Note that the small decrease in Rf around
=4.5 V-1, while Aospec still increases is due to the fact that Cph is increased (and then also Cin) by a decrease in Li in order to maintain the transit time in the diode despite the reduction of Vg1 due to the increase of
. The dynamic range increases as Vdssat1 decreases with
and calls for a high value of
of 5 to 6 V-1 seems a good trade off. Finally, in this range, results shows that it is better in terms of performances (Rf, noise, ...) to take a higher value of
in order to gain on dynamic range margin and then to be able to further decrease the value of
. We then take a
of 6 V-1 and a
of 2 V-1. Modeled performances are summarized in table 2.
Numerical simulations of the designed circuit have then be carried out using Eldo and a BSIMSOI model fitted for the ST transistors. The simulated transimpedance gain is around 600 , while the transimpedance bandwidth is 10 GHz (fig. 14a). We then performed transient simulation of the transimpedance circuit (fig. 14b). The variation of the output voltage, vout related to the 0.1ns width photocurrent pulses confirms that in a simulation point of view, the designed circuit is suitable for 10 Gb/s applications. Noise simulations were also performed with Eldo. Eldo spectral power density of output noise voltage is in very good agreement with Matlab results (fig. 14c). Below a few GHz, the total power densities are dominated by the feedback resistance contribution. Above, the high frequency peak values are related to the low voltage amplifier power densities multiplied by the voltage gain of the amplifier. The equivalent RMS value of the input noise integrated up to 1013 Hz given by Eldo is 1.76A which is in perfect agreement with the 1.75A predicted with Matlab.
4.3. Design of a 1GHz single stage TIA in a 0.5μm SOI CMOS technology and scaling perspectives
In order to compare technologies and draw some conclusions on scaling, we have applied the Matlab model to the design of a 1GHz single stage transimpedance in a fully depleted 0.5 μm SOI CMOS technology . Again we are working at the technology frequency limit here such that the stability limitation prevails compared to the feasibility. The evolution of the performances with
in their principles are very similar to those of the previous design and will not be explained here again. As expected, the most suitable
is near that enabling the maximum gain. Modeled performances are summarized in table 2. When comparing 0.13 and 0.5 μm technologies for the design of 1GHz TIA (see table 1 and table 3), we first notice that the use of a more advanced technology has allowed to use 3 stages instead of one owing to a better ft. This allows for a real increase in performance of the transimpedance (transimpedance gain Zcl increased by more than 16 times, sensitivity improved by 7.5 times). The total transimpedance area should not increase since the use of more stages should be compensated by a reduction of the length of the transistors while the width is about the same. The power consumption is however increased in the 0.13μm technology by a factor of 4. The higher bias current is mainly due to a much higher
ratio and the higher number of stages while these are however partially compensated by the decrease of Vdd. The power consumption can even be reduced by 4 in the 0.13μm design by reducing W1 by 4 and then be equal to the 0.5μm design. In this case Rf but also the input noise will increase leading to a slightly reduced sensitivity of 1.56W (see fig. 9) but still more than 5 times better than the sensitivity of the 0.5μm design. The use of 0.13μm technology also allows for an increase of the photodiode performance (smaller capacitance and higher photosensitive to total area ratio owing to the reduction of the size of the P+ and N+ areas).
In a similar way, the uses of very advanced technology nodes with improved fT, such as the 22nm CMOS one with typical fT of about 400 to 500GHz (improved by about a factor 4 compared to that of a 0.13μm technology), could allow for improving the sensitivity of the receiver at 10GHz by allowing for a multi-stage approach and a further reduction of Cph. Also a single stage 40Gb/s could be attempted. A SOI integrated PIN photodiode with an intrinsic length reduced to below 1μm could fulfill such requirements in terms of transit time cutoff frequency, but with an increased capacitance . This, coupled with the reduced intrinic voltage gain of the single stage amplifier related to the reduced early voltage of ultra short transistor, might result in too low Rf and sensitivity values. To compensate a reduced photodiode total surface but with no reduction of input power (i.e. relying on progress at the emitter side: better focused optical signal, higher power density emission at the source,...) might be necessary.
4.4 Design methodology Summary
To summarize our single-stage top-down design methodology, we have shown that, as the voltage gain is now dependent on Rf, the maximum voltage gain is limited, on one hand, by stability considerations (which usually prevail in weak or moderate inversion regime), and on a second hand, by feasibility considerations (which usually prevail in strong inversion) and that this results on a constraint on W1. The choice of
results from a trade-off between dynamic range and power consumption vs. voltage gain, Rf, noise and then sensitivity performance. The choice of
results on a trade-off between dynamic range, which is maximum towards the weak inversion, and the other performances, which are maximum near the maximum gain (resulting of the stability and feasibility curves) in moderate inversion.
A single-stage 10GHz SVTA Amplifier was realized in the ST 0.13μm SOI CMOS technology. It is co-integrated with a PIN photodiode and a 50 output buffer for the RF measurements (fig. 15a). The latter has a 3mA bias current, a 0.79 voltage gain and a 1A equivalent input noise. Modeled and simulated receiver bandwidths were 10GHz, both before and after insertion of the output buffer. TIA modeled performances are presented in table 4. These expected performances are not as good as those reported in table 2. This is mainly because, in the actual design, we imposed a transit time frequency of the photodiode 1.5 times higher (i.e. 15 GHz) than the bandwidth of the TIA itself in order to make sure to measure the TIA cutoff frequency. This in turn imposed a smaller intrinsic length to the photodiode and a higher diode capacitance. The
's taken for the actual design are also a little bit more conservative, leading to larger value of the widths of M1 and M2 and then to a larger amplifier input capacitance. The total input capacitance is then larger in the implemented design, Rf and Zcl are decreased which in turn also reduces the noise performances of the TIA.
A DC transimpedance gain of 212 was measured which is in very good agreement with the 214 gain predicted by the model. For the AC measurements, we used a modulated 1mW 830 nm laser. The remaining available optical power at the fiber output after modulation and fiber coupling losses was less than 0.01mW which is far below the sensitivity of our receiver and made these measurements impossible. One solution could be to use a femtosecond pulsed laser either at 850nm or 425nm by frequency doubling for example. Because we expected the problem of sensitivity with opto-electrical measurements, we had also designed a "photodiode emulator". The latter was a single transistor voltage amplifier with its output connected at the input of the transimpedance (fig. 15b). The output capacitance of this amplifier was designed to be very similar to that of the PIN diode while its output impedance was kept sufficiently larger than Rf in order to have an equivalent input TIA pole as close as possible to the real case. By varying the gate voltage of the input transistor of this diode emulator, an equivalent photocurrent is created at the TIA input. This allows for the electrical characterization of the TIA bandwidth. A photograph of the chip is shown in Fig 16a. S parameters measurements were done in the 40MHz-40GHz band. These measurements were obtained after a calibration to remove the impedance effect of the RF probes and cables used to connect the device to the spectrum analyzer.
The bandwidth of the TIA is characterized by the S21 parameter which is equal to gma.Zcl.Avout. It is dominated in the frequency band of interest by the transimpedance poles. Avout is the gain of the output buffer which is a little less than one (-1.8dB) in the bandwidth of interest. Measured curve of S21vs. frequency is compared to the Eldo simulated curve in fig. 16b. Both are very similar and have a bandwidth slightly exceeding 10GHz. The few dB difference between the low frequency plateau of S21 is related to a small difference in bias currents. The measured current consumption (equal to 2xIdB+2xId2+Idout) is equal to 5mA while the simulated one is equal to 6mA. This confirms experimentally the ability of 0.13 m CMOS SOI technology for 10Gb/s transimpedance circuits.
In this chapter the design of the transimpedance amplifier, which is the most used receiver front-end for high speed optical applications, has been investigated.
In the Optical Receivers Basics section, the simple resistor system was first presented as well as its limitations. The transimpedance amplifier was then introduced and its basic theory and concepts such as transimpedance gain, bandwidth and stability were derived. Important figures of merit to compare transimpedance amplifiers were also discussed as well as some architectures most often used in the high speed communication area.
Then in the Design of Multistage Transimpedance Amplifiers section, we have presented our top-down methodology to design transimpedance amplifiers in the case where the voltage gain of the voltage amplifier used in the transimpedance amplifier is independent of the feedback resistor Rf. We have shown that this happens when the bandwidth of the transimpedance amplifier is not too close to the transistors frequency limit ft of a given technology and leads to multi-stages approach. Our systematic design procedure was then applied to the design of a 3-stages 1GHz bandwidth transimpedance amplifier in a 0.13 μm PD-SOI CMOS technology. It has allowed us to determine the optimal number of stages (3) to optimize the voltage gain of the amplifier and hence Rf and the transimpedance gain. This maximum voltage gain was shown to be limited by stability considerations. Model Results were validated by Eldo numerical simulations.
Finally, in the Single-stage Transimpedance Amplifier Modeling section, we have presented a top-down methodology to design transimpedance amplifiers when the voltage gain is dependent on Rf. This is the case for very high speed single stage transimpedance amplifiers. In this case we showed that the maximum voltage gain was limited, on one hand, by stability considerations (which usually prevail in weak or moderate inversion regime), and on a second hand, by feasibility considerations (which usually prevail in strong inversion). Our design procedure was applied to the design of a single-stage 10GHz bandwidth transimpedance amplifier in a 0.13 μm PD-SOI CMOS technology and to the design of a 1GHz bandwidth single-stage transimpedance amplifier in a 0.5 μm FD-SOI CMOS technology. Model Results were validated by Eldo numerical simulations and measurements.
Model results for the 3-stage 1GHz bandwidth transimpedance amplifier in a 0.13 μm PD-SOI CMOS technology showed that Cin was very low owing to 1) very good AC performances of thin-film SOI photodiodes (the monolithic integration which avoid bonding capacitor is possible due to the availability of thin-film SOI diodes with 1GHz bandwidth and the very low capacitance of the SOI PIN photodiodes themselves) and 2) the low capacitances of MOS transistors in SOI technology. This fact combined with the high technology
ratio which has enabled the multi-stages approach, has allowed for chosing a very high feedback resistor and then to achieve very high transimpedance gain and low noise operation and this with a very low power consumption. Coupled with the very good responsivity at 405nm (0.25 A/W) and the very low dark current (DC performances) of the thin-film SOI photodiodes, a record sensitivity of 1W (with a BER of 10-12) is projected. This shows the adequacy of 0.13 μm PD-SOI CMOS technology for Blue-DVD applications where the todays specifications are to be able to read input optical power of a few W  but at a 4 times lower bandwidth (250MHz). Coupled with the low responsivity of the thin-film SOI photodiodes at 850nm (0.005A/W), a sensitivity of 50W or -13dBm is still achieved which is considered as an adequate sensitivity receiver for optical communications and comparable to CMOS realization reported in the literature using non integrated diodes with a 90 time better responsivity . This shows the potential interest of this technology for monolithically integrated 1Gb/s optical communication receivers at 850nm or even to realize a blue DVD player which is compatible with the previous red standard.
The design of a 1GHz bandwidth single-stage transimpedance amplifier in a 0.5 μm FD-SOI CMOS technology has allowed us to draw conclusions on the evolution of the performances vs. the CMOS technology scaling down, when compared to the previous design. We first notice that the use of a more advanced technology has allowed us to use 3 stages instead of one owing to its better ft for same TIA bandwidth. This has naturally allowed a real increase of the performances of the transimpedance: transimpedance gain Zcl by more than 16 times, sensitivity improved by 7.5 times, but at a 4 times higher power consumption in the 0.13μm technology. At same power consumption the receiver sensitivity in the 0.13μm technology, if slightly reduced, still remains more than 5 times better than the sensitivity of the 0.5μm design.
Concerning the design of a single stage 10GHz bandwidth transimpedance amplifier in a 0.13 μm PD-SOI CMOS technology, the low Cin, due as previously to the monolithic SOI integration, has enabled us to achieve the highest feedback resistor and one of the highest gain and then the highest transimpedance gain-bandwidth product ZBW (see table 5), as we are achieving one of the highest bandwidth reported for 10Gb/s (theoretically a bandwidth of about 3/4 the data rate is sufficient so that 10 GHz could be related to 13Gb/s operation)). This is achieved without using inductive (LP) or capacitive (CP) peaking techniques which allows to increase ZBW (or the bandwidth for same Rf) but at the expense of chip area (inductors or capacitors to integrate), design complexity, need for tuning... Noise performances are also very good, especially compared to other CMOS designs. The power consumption of the TIA preamplifier (not the complete receiver) is one of the best achieved so far. However, coupled with the low responsivity of thin-film SOI photodiodes at 850nm, a sensitivity of 1.35mW or +1.3dBm is achieved for this monolithically integrated receiver for 10Gb/s optical communications at 850nm. At 405nm on the other hand, the same receiver achieves a high sensitivity of -13dBm. In order to increase the sensitivity at 850nm wavelength however, we can try to increase the diode responsivity. Promising solutions such as the use of SOI CMOS compatible GeOI photodiodes have been discussed in . We can also try to further decrease the transimpedance noise by increasing Rf. With a single-stage approach at a bandwidth of 7.5GHz, our model predicts a 850nm sensitivity of -1.25dBm. Combining this with an avalanche gain of 4 that has been demonstrated with thin-film SOI PIN diodes at 10 Gb/s , adequate sensitivity of at least -7dbm  should be achieved at 10Gb/s. To further improve the sensitivity, we think that the best solution is to attempt a multistage approach so that the voltage gain (and hence ZBW) could be improved. By reducing the bandwidth to about 7.5GHz and using inductive or capacitive peaking if necessary this could be achieved. If not, the uses of very advanced technologies with improved ft, such as 22nm CMOS ones with ft of about 400 to 500GHz (improved by about a factor 4 compared to that of a 0.13μm technology), could allow for improving the sensitivity of the receiver at 10GHz by allowing for a multi-stage approach and a further reduction of Cph. Finally, in such technologies higher data rate could be attempted, e.g. a single stage 40Gb/s. A SOI integrated PIN photodiode with a shorter intrinsic length could fulfill such requirements in terms of transit time cutoff frequency , but with an increased capacitance value. This, coupled with the reduced intrinic voltage gain of the single stage amplifier related to the reduced early voltage of ultra short transistor, might result in too low Rf and sensitivity values. To compensate a reduced photodiode total surface but with no reduction of input power (i.e. relying on progress at the emitter side) might be necessary.
1.AfzalianAryanFlandreDenis2011Design of Thin-Film Lateral SOI PIN Photodiodes with up to Tens of GHz Bandwidth, Advances in Photodiodes, Gian Franco Dalla Betta (Ed.)ISBN: 978-953-307-163-3, InTech153172
15.EmsleyM.K.DosunmuO.UnluM.S.MullerP.LeblebiciY.“Realization of High-Efficiency 10 GHz Bandwidth Silicon Photodetector Arrays for Fully Integrated Optical Data Communication Interfaces”Sept. 16-18EstorilPortugal4750