At the moment, the display market is dominated by liquid crystal displays with amorphous silicon (a-Si) thin film transistor (TFT) backplanes processed on glass. Within the last two years, active matrix OLED (AMOLED) displays have rapidly expanded their market share and are poised to break out of their niche application status. The brightness of OLEDs is current controlled and therefore the driving engine behind every pixel is in its most simple implementation comprising 2 transistors and 1 capacitor (2T1C) as in Figure 1. The required current drive for the necessary brightness (> 500 cd/m2 for cell phone display at > 72 dpi) is however quite challenging for standard a-Si TFTs due to their relatively low mobility (~1 cm2/Vs).
The simplest implementation of a pixel engine for AMOLED current steering is depicted in Figure 1. As a result, each pixel in the display contains 2 transistors and 1 capacitor. Since OLEDs requires current driving, transistor 2 (T2) is used as a current source, whereby the gate-source voltage determines the current level through the OLED. This gate-source voltage is stored on capacitor C and can be modified by selecting transistor 1 (T1) via the row select line. The voltage on the dataline is then transferred to the capacitor.
It is envisioned that the next generation of displays for handheld device will be flexible or even rollable AMOLED displays realized on foils.
The substrate material for backplanes is typically glass, but could be replaced by a flexible substrate, provided that low temperature materials are employed to create the backplane.A working process for OTFTs in a backplane has been shown by Gelinck
Using a high temperature foil like polyimide (PI) which can sustain temperature of <260 °C allows a process flow very similar to the flow used for a-Si backplanes. On the other hand, if a low-temperature, low-cost foil such as polyethylenetheraphtalate (PET) (<120 °C) or polyethylene naphtalate (PEN) (<160 °C) is used, it will necessitate the development of low temperature materials and processes for the backplanes.
To produce a highly efficient OLED display at the end of the process, the choice for a top emitting OLED on top of the pixel engine as shown in Figure 2 is most favorable to generate a larger emitting surface. In order to electrically isolate the OLED from the pixel engine, an interlayer is required. This implements also the necessity to have a connection between the OTFT and the OLED anode. This connection, or via hole, will have to be generated through the interlayers that protect the OTFT from degrading, and ideally without impacting the performance of the OTFT.
The OLED pixels (red, green and blue) will be deposited by evaporation, using a shadowmask patterning technique to create different colors. Prior to this deposition, the anode material has to be deposited and patterned on top of the interlayers. Considering solely performance, the most favorable anode material is silver due to its low resistivity and high reflectivity
There are several challenges in realizing top emitting OLEDs on organic TFTs which have a long lifetime because of their limited chemical, physical and environmental stability. In this chapter, we address processing issues for the interlayers and the anode.
Another issue will be the adhesion of materials on top of each other. Organic materials generally have a pronounced polarity which will act to repel or attract other materials. Another drawback of processing on top of OTFTs is their inherent performance sensitivity to a variety of solvents and their degradation in atmospheric conditions.
2. Interlayer with via process
To obtain the flexibility needed to create a rollable display, OTFTs are one of the possible choices. Among OTFTs, one of the most widely studied and used organic semiconductor materials is pentacene, allowing mobilities up to 1 cm2/(Vs). However, immediately following deposition, oxygen, humidity and solvents will affect the transistor performance adversely. The upper temperature limit the pentacene can sustain is approximately 140 °C; Fukuda
On top of the MIM stack with OTFTs, an insulating interlayer with via holes needs to be processed on which the reflective metal anode of the OLED is photolithographically processed. This interlayer has to allow a good adhesion of the OLED anode, which is deposited last on top of the interlayer through a shadowmask.
In order to have a very smooth anode, the polymer interlayer needs to have a very low surface roughness, since this will be reproduced in the surface of the anode.
The main requirement of the interlayer, that is, to protect the OTFT from air, suggests the use of a material that has good barrier properties against chemicals, moisture and air, a solvent free deposition technique, low temperature budget and good adhesion. When surveying the options available for such an interlayer, a premium choice would be to use poly(p-xylylene), also known as parylene. The deposition of parylene by chemical vapor deposition (CVD) is known to be pinhole free at thicknesses >600 nm, and has been used in many applications in aerospace, electronics and military for its good barrier properties against water, chemicals and oxygen. These properties therefore would be very useful when it comes to protecting the pentacene from degrading. Also the deposition technique is fully compatible with the semiconductor, since the temperature inside the polymerization chamber does not exceed 30 °C over the entire deposition run. Measurements prove the barrier properties of parylene as depicted in Figure 4. After it has been deposited, the parylene polymer can handle temperatures up to 160 °C. When this temperature is exceeded, the polymer will rather degrade and decompose instead of deform.
Parylene itself comes in 3 main derivates; type N, type C and type D, all commercially available. Other types also do exist as commercial products and are chemically modified to be high temperature resistant or have a fluorinated structure. The difference is based on the presence of chlorine atoms on the monomer as depicted below.
This presence of chlorine atoms on the benzene ring has an influence on the surface energy of the resulting film and therefore on the adhesion of subsequent layers. Previous research has shown that the more chlorine atoms that are bonded on the benzene ring, the worse the adhesion towards silver becomes. This can also be seen in contact angle measurements on the different films and therefore, the choice of the N type is best suited for this application. The maximal thickness that was observed by Vicca
To ensure that a silver anode adheres well on the parylene layer, a slow deposition rate, < 1,5 Å/s, is required. This will allow sufficient relaxation time of the silver and reduces stress in the metal film. Stress free layers up to 200 nm are possible with this approach.
Patterning of parylene is done by photolithography using a dry etch plasma to define the desired structures. We used oxygen plasma allowing etch rates up to 17 Å/s using a moderate (50 W) etch power in a reactive ion etch (RIE) plasma. The various parameters such as pressure, gas flows, power, etc., are different for each etch chamber and will not be discussed further.
The CVD process will lead to a conformal coating of the sample, meaning that the polycrystalline structure of the pentacene (with root mean square roughness of 10 nm) is projected into the surface of the parylene and thus, in the surface of the anode.
To decrease the resulting surface roughness, a second spin coated layer over the parylene layer will act as a planarization layer as suggested by Yagi
Considering the requirements (temperature budget <150 °C, crosslinkable and solution processed) there are very few materials available in literature, (e.g. SU8, SC100, photoresist, PVP and PMMA) and after some initial screening experiments, we chose PVP. Having a dielectric constant of around 4.5, this commercially available material has been already used by many research groups as a dielectric in TFT processing, and it has proven to result in smooth surfaces and good adhesion properties. Typically, layer thicknesses around 200 – 400 nm are obtained, covering the parylene film completely without affecting the bending radius of the substrate.
The PVP will not remain on the substrate as a rigid polymer film, but needs crosslinking to form a film that is compatible with chemicals used in further processing. To enable this cross linking, a molecule will bond on the separate PVP polymer chains and create a chemically inert film. The cross linker most commonly used for PVP is poly(melamine-co-fromaldehyde). A process flow is described by Hwang
When lowering the cross linking temperature to a more acceptable 145 °C, the cross linking time increased to almost 3 hours. When using this long time for a baking process, it is important to allow the substrate a long cool down period afterwards to prevent stress effects. These stress effects can be seen by bended wafers, which will result in misaligned structures. The use of low temperature cross linkers has been described in literature and can be used for further decreasing of the temperature.
Other ways for decreasing the crosslinking temperature even further were investigated and reported by Vicca
Another point that needs to be taken into account is the cross linking reaction itself between the polymer chains and the cross linking molecule. Very often this reaction produces side products such as ions or volatile organic compounds (VOC) or else unused cross linker remains behind. These molecules will very often function like as a charge trap, influencing the transistor characteristics and which has been observed for both crosslinking molecules.
Typical effects that can be seen in the transfer characteristic curves are hysteresis, indicating the presence of charge trapping ions, often left from reaction side products or VOC. This might indicate a need for a longer bake time to evaporate these products out of the film. If the threshold voltage (Vt) shifts in the negative direction, this indicates an excessive amount of cross linker. To solve this effect, a lower percentage of the cross linker should be used. Using these indications, a good recipe for PVP can be optimized.
Once the resist is patterned, dry etching with oxygen plasma (RIE) will remove the PVP accurately. Just like when etching parylene, the discussion on different parameters like flows, power, pressure, etc., will not be applicable here, since this is very dependent on etch chamber architecture.
3. Silver anode
To find the optimal material that can be used as an anode material, the different properties of possible candidates must be compared to ensure that the best option is used for the process. Considering that the most advanced OLED stacks have doped- transport/injection layers implemented, the choice of work function is not strongly relevant. To increase the output of the OLED, it would be useful to reflect the light that is emitted towards the backside of the stack. This efficiency increment can be realized by choosing a highly reflective metal that also can be deposited with a sufficient thickness such that it is not transparent. To ensure these thick layers are possible on top of the polymer interlayer, a good degree of adhesion is required to prevent the metal from delaminating.
In Figure 9, a comparison between different metals is made to compare the light intensity with the intensity of the silver, It is clearly shown that the silver always has the highest intensity and also the highest reflectance. This was also calculated for red and blue OLED stacks in Figures 10 and 11, respectively.
From a performance point of view, Ag emerges as the optimal choice. In addition, the deposition of the silver anode on PVP or parylene does not require any adhesion layers or adhesion promotors such as HMDS since silver has a good adhesion on the polymer surfaces.
3.1. Lift off
Once the silver layer has been deposited, it still needs to be patterned in order to define the separate pixels in the display. For patterning, the main options available are lift off or etching. When using a lift off process, the resist will already be patterned on the wafer prior to the silver deposition and will be dissolved afterwards in a solvent to remove the silver where it has no contact with the polymer interlayer.
However, for yield consideration, lift-off processes should be generally avoided and since the inherent limit to the metal thickness is approximately 50 nm, it would not be compatible with the non-transparent silver layer (200 nm) that is desired.
Another disadvantage of the lift off process is the long exposure of the wafer and OTFTs to the lift off solvent(s). It is proven by measuring mobilities of OTFTs that were encapsulated with different polymers and immersed for 1 minute in various solvents, that liquid chemicals used in general processing do have a negative impact on the mobility. Results of these tests are showed in Figure 13, using 2 types of polymer to protect the OTFTs from the chemicals.
3.2. Wet etching
When looking at the option to pattern the anode layer with an etch process, the etching is performed after a silver layer has been deposited and patterned by photolithography using the inverted mask lay out of the lift off patterning. The etching itself can be done by wet etch or dry etching. If a wet etch process is used, a certain amount of reproducibility should be respected. To do this, the EDC system by Laurell Inc. was used, employing a commercial silver etchant. The system will spin the wafer while the etchant is sprayed over the wafer, causing the etching of the silver. The main issue with this system is to find a good rotation speed for the spinner. If the wafer rotates too slowly, the etchant arriving in the center will remain for too long and cause over etching here. If the resolution of the etched structures is monitored as shown in Figure 14, the ideal spin speed would be around 1500 rpm. At this equilibrium point, the overertch in the center and at the wafer edge was found to be the same. Adjusting the etch time leads to the desired amount of overetch, which is as close to zero as possible. Doing this however leaves a very small time window for the etching, resulting in a 7 second etch time for 200 nm of silver.
The main problem however of the wet etch technique is again the use of liquids. This can be seen by microscope inspection of the pixels after patterning. The swelling of the interlayer underneath will deform the pixel surface dramatically as can be seen in Figure 15, leading to pixel failures.
The liquid impact can also be observed in the performance of the transistors by comparing their mobilities before and after the silver has been patterned.
3.3. Dry etching
When looking to dry etching techniques, literature describes only few effective etching techniques for the removal of silver. These processes were typically used to pattern silver lines in circuit purposes and the use of an inductively coupled plasma (ICP) is the most common technique described by Lee
The purpose of this mixture is the fluorination of silver by CF4, followed by argon sputtering in order to remove the silver salt.
We tried to produce a dry etch process running on a reactive ion etch (RIE) fab tool. At first, the effect of pure gasses present in the tool was tested to see their effect on a pristine silver film, deposited on a polymer coated wafer that could act as a dummy for the stack that will be used later. The gasses that can be used are argon, CF4, oxygen and SF6.
When using a pure argon gas plasma, the ionized argon atoms (Ar+) will sputter on the silver surface, causing a rough surface, but without removal of silver. As a side effect of this sputtering, the temperature of the substrate increases too much to allow the use of argon when a foil substrate is used.
Using an oxygen plasma, the reaction with silver is obvious to be observed and results in a highly affected surface. This etching will eventually remove all silver without generating too much heat, but the removal of silver is caused by a stress induced exfoliation. The oxygen will react with the silver and create silver oxides which have a certain amount of stress in them.
This stress will lead to the creation of flakes of silver oxide that will exfoliate from the surface because of their different expansion coefficient. The size of these flakes cannot be controlled and will result in low resolution if this gas only is used for the removal of silver. This observation has also been described in literature by Nguyen
Etching silver with a CF4 plasma will result in a thin layer of silver fluoride which will be present on the top layer of the surface, but will act more similar to a passivation layer that prevents further fluorination of the metal. This is also why a mixture of CF4 and argon is needed to remove this top layer such that a fresh silver layer is exposed to the CF4 gas.
The use of an SF6 plasma will result in a gently affected silver layer in which probably some fluorination has occurred, but in which also sulfur depositions can be observed as yellow dots.
Since the use of a single gas appears not to be possible, a similar gas mixture as used in ICP appeared more useful. As a starting point, the same Ar/CF4 mixture as described in literature can be tested, but will result in a non effective etch. Probably due to a low etch power (500 W) compared with ICP etch power (1500 W), this will not be suitable for RIE tools. To get the mixture working, the energy needed to start the fluorination needs to be lowered. To do this, a certain amount of oxygen can be added to the Ar/CF4 mixture, which will react first with the silver layer due to its favored reactivity. This will result in a silver oxide that will be easily accessible for the CF4 gas to fluorinate it further into silver fluoride which can be sputtered away by the argon ions.
To understand what the right amount of oxygen in the Ar/CF4 mixture is, samples with silver will be used again to verify the impact of different gas flows. In principle, the Ar/CF4 mixture will be present in excessive amounts that will fluorinate immediately all silver oxide formed by the oxygen. Afterwards, the end product will be removed by the Ar+ ions sputtering.
When the amount of oxygen is too low, the silver will not etch completely and remains on the substrate.
Using too much oxygen will cause etching of the underlying polymer interlayer once the silver film has been removed.
If the right amount of oxygen is used in the mixture, the polymer interlayer will appear shiny as it was deposited before the silver deposition and all silver will be removed from the sample.
The compatibility of a dry etch recipe with that of the resist also requires optimization. The effect of a too high etch power will result in a carbonization of the resist and will not allow subsequent stripping of the resist with solvents. Also, the heating of the substrate will be reduced as the etch power is reduced.
If the etching would take too long, this will also affect the resist adversely, leading to the removal of the resist. This is mainly caused by the presence of oxygen in the gas mixture.
All the parameters were optimized for our tool and will of course depend from etch chamber to etch chamber. In our etch chamber, etch rates of ±13Å/s were obtained without affecting or removing a commercial photoresist used for the patterning of pixels.
To confirm that the dry etch technique has not affected the performance of the OTFTs, electrical measurements were executed on several transistors on different wafers and mobilities were calculated. This resulted in an average mobility at the end of the process of 0.18 cm2/(Vs). When the final mobility is calculated for the OTFTs before and after the dry etch process step, 61% of the mobility has been preserved. This was also calculated for the wet etch technique, resulting in a final mobility 28% of the original mobility, showing the advantage of dry etch in terms of both transistor stability and resolution.
Furthermore, when comparing the transfer curves of the OTFTs depicted in Figure 26, it can be seen that there is no loss of uniformity over the processing steps, which is also one of the beneficial effects of the dry etch recipe.
After OLED depositions were finished, 1 cm2 test pixels as depicted in Figure 27 show a high degree of uniformity of color indicating a smooth surface and giving an efficient light output of 83 cd/A for a green OLED and 37 cd/A for a red OLED.
When the active pixels are connected to a control box, the pixels in the display will switch on and off according to the commands of the controller. This allows us to activate or deactivate all pixels or switch on even or odd rows and/or columns or to make checker board patterns as is shown in Figure 28.
To tackle the challenges of a low temperature process for making organic backplanes for OLED displays, the use of different polymers in the interlayer, parylene as well as PVP, has been optimized in terms of their deposition, patterning and subsequent materials that will be deposited on them. Working transistors prove the quality of the materials and the efficiency of the process.
For the metal anode, a choice for silver was made mainly based on its excellent reflection and conductivity properties. The patterning of the silver anode is performed by dry etching using an optimized RIE process. This was developed due to the fact that other etch methods seemed to affect the whole stack adversely and the output of OTFT at the end.
Combining the experience and technology that has been gained over the research on the different interlayers and their appropriate processing techniques has led to the realization of high efficiency OLED pixels.
This work was realized in the framework of the EC project FLAME FP7 ICT-216546 in collaboration between imec, TNO/HOLST centre, Polymer Vision and FraunhoferIPMS. I would like to thank K. Fehse for the simulated light output data for different anode materials and my colleagues at imec and in the HOLST centre for their support in this work.
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