Open access

Optoelectronic Device using a Liquid Crystal Holographic Memory

Written By

Minoru Watanabe

Published: 01 November 2009

DOI: 10.5772/9687

From the Edited Volume

New Developments in Liquid Crystals

Edited by Georgiy V Tkachenko

Chapter metrics overview

3,068 Chapter Downloads

View Full Metrics

1. Introduction

Recently, the technologies related to liquid crystal spatial light modulators have progressed dramatically [1]–[4]. Such modulators are classifiable as two types: transmissive and reflective. Both types are used widely for various applications, e.g. liquid crystal television panels, personal computer displays, and projector systems. In particular, the resolution of the latest liquid crystal spatial light modulators in projectors has reached 1,920 pixels 1,080 pixels, the pixel size of which has also reached 8.5 m 8.5 m [1], [2] as portrayed in Fig. 1 and Table 1. Therefore, their current resolution and pixel size make them available for use as holographic media.

Figure 1.

Photograph of a liquid crystal – spatial light modulator (LC-SLM). The modulator is an LCD panel (L3D07U-81G00 Seiko Epson Corp.)

LCD type L3D07U-81G00
Resolution 1,920 x 1,080
Panel size
Pixel pitch 8.5 m
Aperture ratio 55 %

Table 1.

Specifications of the L3D07U-81G00 LC-SLM Panel.

Moreover, recently, optically reconfigurable gate arrays (ORGAs) with a holographic memory have been developed [5]–[7], [11]–[14], [21]–[23]. The gate array of this optoelectronic device has a fine grain gate array structure similar to those of field programmable gate arrays (FPGAs) [8]–[10]. Computations or circuit operations on the gate array are executed electrically, as they are on FPGAs, whereas configurations and reconfigurations for the gate array are optically executed. The ORGA architecture has features of rapid reconfiguration and numerous reconfiguration contexts. Such an optical reconfiguration architecture often uses liquid crystal spatial light modulators as holographic memory media [11]–[14], [21]–[23].

Therefore, this chapter first presents the characteristics of a liquid crystal holographic memory to generate binary patterns. In addition, as an illustration of one application of liquid crystal devices, this chapter presents discussion of the research of optically reconfigurable gate arrays (ORGAs).


2. Transmissive-type computer-generated hologram

2.1. Calculation of a holographic memory

This section presents a description of a transmissive-type computer-generated hologram that can provide two-dimensional binary patterns. Figure 2 presents coordinates of a hologram plane and an observation plane. Both planes are placed in parallel at a distance of L. The observation plane is given by the coordinate (x, y); the holographic plane is given by the coordinate (x0,y0). An incident light for the holographic memory is assumed as a collimated monochromatic laser source. The collimated laser beam is incident from the left side of the holographic memory plane.

Figure 2.

Coordinates for diffraction from a liquid crystal holographic memory.

Here, a two-dimensional binary pattern on the observation plane is assumed to be given as a function O(x,y), which represents a configuration or reconfiguration context in optically reconfigurable gate arrays (explained later). At that time, the intensity distribution of a holographic medium is calculable using the following equations.

H ( x 0 y 0 ) O ( x y ) sin ( 2 π λ r ) d x d y r = L 2 + ( x 0 x ) 2 + ( y 0 y ) 2 E1

In those equations, signifies the wavelength, L signifies the distances between the holographic plane and the observation plane, and r stands for the distance between the point source P ( x 0 y 0 ) on the holographic memory plane and the point of observation Q ( x y ) . The distance L is expected to take ( n + 1/4) λ , where n is an arbitrary natural number, to receive the perpendicular incident beam on the observation plane efficiently with the shortest distance from the holographic memory plane. The value H ( x 1 y 1 ) is normalized as 0–1 for the minimum intensity H m i n and maximum intensity H m a x , as shown below.

H ( x 0 y 0 ) = H ( x 0 y 0 ) H m i n H m a x H m i n E2

Finally, the normalized image H is used for implementing a holographic memory.

2.2. Diffraction from a holographic memory

Next, the diffraction pattern is estimated from the above calculated holographic memory pattern. The complex light distribution at the coordinate (x, y) are calculated using the following equations as

u ( x y ) Y m i n Y m a x X m i n X m a x H ( x 0 y 0 ) exp ( i 2 π λ r ) d x 0 d y 0 r = L 2 + ( x 0 x ) 2 + ( y 0 y ) 2 E3

where H ( x 0 y 0 ) denotes the calculated and normalized holographic memory pattern, represents the wavelength, L stands for the distances between the holographic plane and the observation plane, and X max , X min , Y max , and Y min respectively represent the holographic memory sizes. Finally, the diffraction intensity from a holographic memory is calculable as

I ( x y ) = u ( x y ) u * ( x y ) E4

where the superscript asterisk denotes the complex conjugate.

2.3. Single bright bit example in the Fresnel region

In this section, once again, the holographic memory pattern described in section 2.1 is treated, but in the Fresnel region. If distance L between the two coordinate planes can be assumed to be large compared with the sizes of a holographic memory and observation area, when the following condition is satisfied,

1 4 λ { ( x 0 x ) 2 + ( y 0 y ) 2 } 2 L 3 E5

then r can be approximated to

r L + ( x 0 x ) 2 + ( y 0 y ) 2 2 L E6

where (x0,y0) is the coordinate of the holographic memory plane and (x,y) is the coordinate of the observation plane. Here, assuming that the condition L= ( n + 1/4) λ (n = an arbitrary natural number) is satisfied, then ( n + 1/4) λ can be substituted into the first term L of Eq. 6 shown above. Then, substituting Eq. 6 with the condition into Eq. 1, the following equation is accomplished.

H ( x 0 y 0 ) O ( x y ) cos ( π λ L { ( x 0 x ) 2 + ( y 0 y ) 2 } ) d x d y E7

Assuming that the single bright bit is located on the coordinate ( α β ) , the equation O(x,y) can be considered as δ ( x α y β ) . The two-dimensional Dirac delta function δ ( x y ) is defined as shown below.

δ ( x y ) = { f o r x = y =0 0, o t h e r w i s e E8
δ ( x y ) d x d y =1 E9
When O ( x y ) = δ ( x α y β ) , Eq. 7 can be simplified to the following equation.
H ( x 0 y 0 ) cos ( π λ L { ( x 0 α ) 2 + ( y 0 β ) 2 } ) E10

The maximum and minimum of the above equation are, respectively, 1 and -1. Therefore, the above equation can be substituted into Eq. 2. Finally, the following equation of a holographic memory pattern including a single bright bit in Fresnel region can be derived.

H ( x 0 y 0 ) = 1 2 cos ( π λ L { ( x 0 α ) 2 + ( y 0 β ) 2 } ) + 1 2 E11

This equation represents a Fresnel zone lens, the center of which is located at coordinate ( α β ) . An example of a holographic memory of size of 1.632 mm 1.632 mm to generate a single bright bit is shown in Fig. 3. In this example, the holographic memory pattern was calculated using the condition that the target laser wavelength is 532 nm, the distance L is 100 mm, and the coordinate ( α , β ) of a bright bit is (0, 0).

Figure 3.

Holographic memory pattern to generate a single bright bit. The size of the holographic memory pattern is 1.632 mm 1.632 mm. The target laser wavelength is 532 nm. The distance L is 100 mm. The coordinate ( α , β ) of a bright bit is (0, 0).

It can be confirmed that the holographic memory pattern represents the Fresnel zone lens. Therefore, a holographic memory pattern to generate a two-dimensional binary pattern with multi-bright bits becomes a superimposition of the Fresnel zone lens. Next, the diffraction pattern from the Fresnel zone lens is estimated. The complex light distribution at the coordinate (x, y) is calculated using the following equation.

u ( x y ) Y m i n Y m a x X m i n X m a x { cos ( π λ L { ( x 0 α ) 2 + ( y 0 β ) 2 } ) + 1 } E12
× exp ( i π λ L { ( x 0 x ) 2 + ( y 0 y ) 2 } ) d x 0 d y 0 E13

Therein, is the wavelength, L signifies the distances between the holographic plane and the observation plane, and X max , X min , Y max , and Y min respectively represent the holographic memory sizes. Finally, the diffraction intensity from a holographic memory is calculable as follows.

I ( x y ) = u ( x y ) u * ( x y ) E14

Therein, the superscript asterisk denotes the complex conjugate. To produce a compact system, the system parameters are not always in the Fresnel region. Therefore, at that time, the Fresnel approximation is inapplicable for calculations and Eqs. 1, 2, 3 and 4 must be used. However, when the system parameters are in the Fresnel region, the approximation described above is useful for holographic memory estimations.


3. Optically Reconfigurable Gate Array (ORGA)

Among applications using liquid crystal devices, studies of Optically Reconfigurable Gate Arrays (ORGAs) exist. Such an ORGA is an optoelectronic device using a liquid crystal device as a holographic memory. This device is being developed as an alternative device of current VLSIs or as a next-generation general-purpose programmable VLSI. The following section presents a description of the ORGA background and architecture.

3.1. Background

In recent years, SRAM-based Field Programmable Gate Arrays (FPGAs) have been used widely for large-item small-volume production because of their flexible programmable capabilities [8]–[10]. Moreover, demand for high-speed reconfigurable devices has been increasing. If circuit information can be downloaded rapidly from a configuration memory, idle circuits on a gate array can be removed. At that time, other necessary circuits can be downloaded from the configuration memory into the gate array, thereby increasing the gate array's activity. In so doing, high-speed dynamic reconfiguration can increase the performance of programmable gate arrays. However, since reconfiguration of FPGAs requires more than several milliseconds, FPGAs are unsuitable for use as dynamically reconfigurable devices [8]–[10].

However, high-speed reconfigurable devices have been developed: DAP/ DNA chips, DRP chips, and multi-context FPGAs [15]–[20]. Those devices package reconfiguration memories and microprocessor arrays or gate arrays onto a chip. The internal reconfiguration memory stores reconfiguration contexts of 4–16 banks, which can be changed from one to another on a clock. Consequently, the arithmetic logic unit or gate array of such devices can be reconfigured on every clock cycle in a few nanoseconds. Nevertheless, an important problem remains: simultaneously increasing the internal reconfiguration memory while maintaining the gate density is extremely difficult.

For that reason, optically reconfigurable gate arrays (ORGAs) [5]–[7], [11]–[14], [21]–[23] have been developed to provide two capabilities: rapid reconfiguration and numerous reconfiguration contexts. Such optical reconfiguration architecture often uses liquid crystal spatial light modulators as a holographic memory [11]–[14], [21]–[23]. This chapter presents a description of the studies of ORGAs with a liquid crystal spatial light modulator.

3.2. Entire construction

An overview of an Optically Reconfigurable Gate Array (ORGA) is shown in Fig. 4. An ORGA consists of a gate-array VLSI (ORGA-VLSI), a holographic memory, and a laser diode array. The holographic memory can store numerous reconfiguration contexts. A laser array mounted on the top of the holographic memory addresses the reconfiguration contexts. The diffraction pattern from the holographic memory can be received as a reconfiguration context on a photodiode-array of a programmable gate array on an ORGA-VLSI. Such ORGA architecture enables microsecond-order reconfiguration and multiple reconfiguration contexts. Therefore, virtually, the architecture can achieve gate counts larger than the physical gate count on a VLSI.

3.3. Gate array structure

The basic functionality of an ORGA-VLSI is fundamentally identical to that of currently available field programmable gate arrays (FPGAs). Figure 5 depicts the gate array structure of a first prototype ORGA-VLSI. The ORGA-VLSI chip was fabricated using a 0.35 m triple-metal CMOS process [12]. A photograph of the board is portrayed in Fig. 6. The specifications are presented in Table 2. Here, the fundamental function of an ORGA-VLSI is

Figure 4.

Overview of an ORGA.

Technology 0.35 m double-poly triple-metal CMOS process
Chip size
Photodiode size 25.5 m 25.5 m
Distance between photodiodes 90 m
Number of photodiodes 340
Gate count 68

Table 2.

ORGA-VLSI Specifications

described using this chip design as an example of ORGA-VLSI chips. The ORGA-VLSI chip consists of 4 optically reconfigurable logic blocks (ORLB), 5 optically reconfigurable switching matrices (ORSM), and 12 optically reconfigurable I/O bits (ORIOB) portrayed in Fig. 5(a). Each optically reconfigurable logic block is surrounded by wiring channels. One wiring channel has four connections. Switching matrices are located on the corners of optically reconfigurable logic blocks and are used as switches of wiring channels. In turn, the function of each block is described in the following sections.

3.3.1. Optically reconfigurable logic block

A block diagram of an optically reconfigurable logic block is presented in Fig. 5(b). Each optically reconfigurable logic block consists of a four-input one-output look-up table (LUT), six multiplexers, four transmission gates, and a delay flip-flop with a reset function. The input signals from the wiring channel, which are applied from optically reconfigurable I/O blocks, are transferred to a look-up table through four multiplexers. The look-up table is used for implementing Boolean functions such as AND circuits, OR circuits, and XOR circuits. The look-up table construction can be considered as a static memory. For example, a four-input one-output look-up table can be considered as a static memory with a four-bit address bus and a single-bit data bus. In this case, the address bus and data bus of the memory respectively represent signal inputs and signal output of a logic circuit. If some configuration information, "0001XXXXXXXXXXXX" is programmed to the static memory (X signifies a do not care state), then the look-up table can function as a two-input one-output

Figure 5.

Gate-array structure of a fabricated ORGA. Panels (a), (b), (c), and (d) respectively depict block diagram of a gate array, an optically reconfigurable logic block, an optically reconfigurable switching matrix, and an optically reconfigurable I/O bit.

Figure 6.

Photograph of an ORGA-VLSI board with a fabricated ORGA-VLSI chip. The ORGA-VLSI was fabricated using a 0.35 m three-metal 4.9 4.9 mm2 CMOS process chip. The gate count of a gate array on the chip is 68. In all, 340 photodiodes are used for optical configurations.

AND circuit. In this case, two multiplexers connected to upper two bits of the look-up table must be programmed to be L. The multiplexers connected to the inputs of look-up table can choose L, H, and two signals of the wiring channel for the look-up table inputs. In addition, the output of the look-up table is connected to a multiplexer through a delay type flip-flop. Therefore, a combinational circuit and sequential circuit can be chosen by changing the multiplexer. Finally, an output through the multiplexer from the look-up table is connected to the wiring channel through transmission gates, again. The last multiplexer controls the reset function of a delay-type flip-flop. Such a four-input one-output look-up table, each multiplexer, and each transmission gate respectively have 16 photodiodes, two photodiodes, and one photodiode. In all, 32 photodiodes are used for programming an optically reconfigurable logic block. In Fig. 5(b), the P mark shows a photodiode. In this optically reconfigurable logic block, although eight other photodiodes were implemented for special use of a differential reconfiguration strategy, that method is described in earlier reports [12], [21].

3.3.2. Optically reconfigurable switching matrix

Similarly, optically reconfigurable switching matrices are optically reconfigurable. A block diagram of the optically reconfigurable switching matrix is portrayed in Fig. 5(c). The basic construction is the same as that used by Xilinx Inc. One four-directional with 24 transmission gates and 4 three-directional switching matrices with 12 transmission gates were implemented in the gate array. In this construction, a connection in any direction can be realized using a transmission gate so that propagation delay can be decreased compared with the case using four transmission gate passes. Each transmission gate can be considered as a bi-directional switch. A photodiode is connected to a transmission gate and controls whether the transmission gate is closed or not. Based on that capability, four-direction and three-direction switching matrices can be programmed, respectively, as 24 and 12 optical connections.

3.3.3. Optically reconfigurable I/O block

Optically reconfigurable gate arrays are assumed to be reconfigured frequently. For that reason, an optical reconfiguration capability must be implemented for optically reconfigurable logic blocks and optically reconfigurable switching matrices. However, the I/O block might not always be reconfigured under such dynamic reconfiguration applications because such a dynamic reconfiguration arises inside the device and each state of Input, Output, or Input/Output, and each pin location of the I/O block must always be fixed because of limitations of an external environment. However, the ORGA-VLSI support optical reconfiguration for I/O blocks because optical reconfiguration information is provided optically from a holographic memory in ORGA. Consequently, electrically configurable I/O blocks are unsuitable for ORGAs. Here, each I/O block is also controlled using nine optical connections. Always, the configuration of the optically reconfigurable I/O block is executed only initially.

3.3.4. Physical implementation

Because the ORGA-VLSI has 340 photodiodes to program its gate array, the ORGA-VLSI can be reconfigured rapidly and perfectly in parallel. In this fabrication, the distance between each photodiode was designed as 90 m. The photodiode size is set as 25.5 25.5 m2 to ease optical alignment. The photodiode was constructed between the N-well layer and P-substrate. The gate array's gate count is 68. It was confirmed experimentally that the ORGA-VLSI itself is reconfigurable within 10 ns.


4. Nine-configuration-context ORGA

This section presents an implementation example of a nine-configuration context ORGA.

4.1. Experimental system

An ORGA holographic memory system with nine configuration contexts using a liquid-crystal spatial light modulator (LC-SLM) as a holographic memory, nine 532 nm, 300 mW lasers (in the actual implementation, one laser emulated the nine lasers), and an ORGA-VLSI are depicted in Fig. 7. Each laser corresponds to a configuration context or a holographic recording area including the single configuration context and is used for addressing the configuration context. First, a nine-context holographic memory pattern is calculated using Eqs. 1 and 2. Here, distance L between a holographic memory and an ORGA-VLSI is 100 mm. The wavelength is 532 nm. The target LC-SLM is a projection TV panel (L3D07U-81G00; Seiko Epson Corp.). It is a 90 twisted nematic device with a thin-film transistor. The panel has 1,920 1,080 pixels, each of 8.5 8.5 m2, with 256 gradation levels. The calculated holographic pattern shown in Fig. 8(a) is displayed on the LC-SLM. The number of pixels of each recording area, including one reconfiguration context, is 450 250. Each interval between recording areas is 5 pixels. Therefore, the entire holographic memory pattern is 1,360 pixels 760 pixels. Each laser beam is collimated: the beam is incident to its corresponding holographic recording area on the LC-SLM. By turning on a certain laser, one configuration context can be programmed onto the ORGA-VLSI. Optically parallel programming enables very high-speed configuration and reconfiguration.

Figure 7.

ORGA system using a liquid crystal spatial light modulator as a holographic memory.

Figure 8.

a) Holographic memory pattern, and CCD-captured images of configuration contexts of (b) an AND and (c) a NOR circuits.

4.2. Configuration experiments

Here, among the nine configuration contexts, two configuration experiments of an AND circuit and a NOR circuit are introduced. A configuration context of an AND circuit was programmed at the top-left side of the holographic memory, while a configuration context of a NOR circuit was programmed at the bottom-left side of the holographic memory. Figures 8(b) and 8(c) depict CCD-captured images of configuration contexts of the AND circuit and the NOR circuit at the position of the ORGA-VLSI. Figure 9 shows that the AND circuit was programmed correctly onto ORGA-VLSI and that the AND circuit functioned correctly. Here, the configuration period of the AND circuit is 5 s. Figure 10 shows that the NOR circuit was programmed correctly onto ORGA-VLSI and that the circuit functioned correctly. The configuration period of the NOR circuit was measured as 4 s, thereby confirming the rapid configuration capability of the nine-configuration-context ORGA architecture.

Figure 9.

s configuration result of an AND circuit.

Figure 10.

s configuration result of an NOR circuit.

4.3. Response time of the liquid-crystal holographic memory

Next, the response time of a liquid-crystal holographic memory is estimated. The turn-on and turn-off times were measured experimentally using an L3D07U-81G00 panel provided by Seiko Epson Corp. The results show that the turn-on time is less than 12 ms. The turn-off time is less than 2 ms, as shown in Fig. 11.


5. Acceleration method

A liquid-crystal holographic memory is an easily rewritable material. For that reason, many reconfiguration contexts can be supplied dynamically to a gate array. Of course, a liquid


Figure 11.

Response time measurement of a liquid crystal holographic memory. The turn-on and turn-off times were measured experimentally using an LCD panel (L3D07U-81G00; Seiko Epson Corp.) Results show that the turn-on time is less than 12 ms; the turn-off time is less than 2 ms.

crystal holographic memory requires a period of a few milliseconds for changing holographic contexts. However, once a liquid-crystal holographic memory stores a holographic configuration context array, the holographic memory can successively write configuration contexts of the holographic configuration context array onto the gate array. Consequently, although a context preparation for a liquid-crystal holographic memory takes a long time, once it is completed, rapid configurations can be done easily. The average configuration time becomes the value of the response time of the liquid-crystal holographic memory divided by the array number of holographic configuration context array if it is assumed that the laser reconfiguration period is negligible compared to the response time of a liquid-crystal holographic memory. Therefore, when each configuration time T Conf. is much smaller than the switching time T LC of a liquid-crystal holographic memory, the equation is estimated as the following.

T V i r t u a l c y c l e T L C N E15

As configuration contexts become more numerous in the future, this architecture is expected to become increasingly useful.


6. Conclusion

This chapter has described an optically reconfigurable gate array (ORGA) with an LC-SLM and a reconfiguration-speed acceleration method. The ORGA architecture has enabled the achievement of microsecond-order reconfiguration and nine configuration contexts. Although the LC-SLM response time is not faster than that of silicon devices, the use of multiple configurations decreases the average configuration period. Based on that improvement, this easily programmable LC-SLM was demonstrated as useful for ORGA applications.



This research was supported by the Ministry of Education, Science, Sports and Culture, Grant-in-Aid for Scientific Research on Innovative Areas, No. 20200027. The VLSI chip in this study was fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Rohm Co. Ltd. and Toppan Printing Co. Ltd. Also, some experiments were supported by Mr. M. Nakajima and Mr. T. Mabuchi.


  1. 1. Takuya Otani 2006 "Seiko Epson Develops New Liquid Crystal Panel for Rear Projection TV," Nikkei Electronics,.
  2. 2. SEIKO EPSON CORPORATION, 2006 "Epson Develops Next-Generation HTPS Panel for LCD Projection TVs," News Release,.
  3. 3. Sony Corporation, 2003 "Sony develops "SXRD", a display device capable of generating high resolution, high contrast images of film quality smoothness," Press Releases,.
  4. 4. Canon Incorporated, 2008 "CANON ANNOUNCES DEVELOPMENT OF OWN LCOS REFLECTIVE LCD PANEL," Press Release,.
  5. 5. Mumbru J. Panotopoulos G. Psaltis D. An X. Mok F. Ay S. Barna S. Fossum E. 2000 "Optically Programmable Gate Array," SPIE of Optics in Computing 2000, 4089 763 771 ,.
  6. 6. Mumbru J. Zhou G. An X. Liu W. Panotopoulos G. Mok F. Psaltis D. 1999 "Optical memory for computing and information processing," SPIE on Algorithms, Devices, and Systems for Optical Information Processing III, 3804 14 24 ,.
  7. 7. Mumbru J. Zhou G. Ay S. An X. Panotopoulos G. Mok F. Psaltis D. 1999 "Optically Reconfigurable Processors," SPIE Critical Review 1999 Euro-American Workshop on Optoelectronic Information Processing, 74 265 288 ,.
  8. 8. Altera Corporation, "Altera Devices," http://www.
  9. 9. Xilinx Inc. "Xilinx Product Data Sheets," http://www.
  10. 10. Lattice Semiconductor Corporation, 2005 "LatticeECP and EC Family Data Sheet," http://www.,.
  11. 11. Watanabe M. Kobayashi F. 2006 "Dynamic Optically Reconfigurable Gate Array," Japanese Journal of Applied Physics, 45 4B 3510 3515 ,.
  12. 12. Miyano M. Watanabe M. Kobayashi F. 2007 "Optically Differential Reconfigurable Gate Array," Electronics and Computers in Japan, Part II, 11 90 132 139 ,.
  13. 13. Yamaguchi N. Watanabe M. 2008 "Liquid crystal holographic configurations for ORGAs," Applied Optics, 47 28 4692 4700 ,.
  14. 14. Seto D. Watanabe M. 200 2008"A dynamic optically reconfigurable gate array- perfect emulation," IEEE Journal of Quantum Electronics, 44 5 493 500 ,.
  15. 15. Ipflex Inc.
  16. 16. Nakano H. Shindo T. Kazami T. Motomura M. 2003 "Development of dynamically reconfigurable processor LSI," NEC Tech. J. (Japan), 56 4 99 102 ,.
  17. 17. Dehon A. 1996 "Dynamically Programmable Gate Arrays: A Step Toward Increased Computational Density," Fourth Canadian Workshop on Field Programmable Devices, 47 54 ,.
  18. 18. Scalera S.M. Vazquez J.R. 1998 "The design and implementation of a context switching FPGA," IEEE symposium on FPGAs for Custom Computing Machines, 78 85 ,.
  19. 19. Trimberger S. et al. 1997 "A Time--Multiplexed FPGA," FCCM, 22 28 ,.
  20. 20. Jones D. Lewis D. M. 1995 "A time--multiplexed FPGA architecture for logic emulation," Custom Integrated Circuits Conference, 495 498 ,.
  21. 21. Nakajima M. Watanabe M. 2009 "Fast reconfiguration experiments of an optically differential reconfigurable gate array with 9 configuration contexts, IEEE International Symposium on Circuits and Systems, 2013 2016 ,.
  22. 22. Nakajima M. Watanabe M. 2009 "Fast optical reconfigurations of a nine-context DORGA," International Workshop on Applied Reconfigurable Computing, 5453 123 132 ,.
  23. 23. Mabuchi T. Watanabe M. 2008 "A 9-context Optically Reconfigurable Gate Array," International SoC Design Conference, 1 4 ,.

Written By

Minoru Watanabe

Published: 01 November 2009