Values of the lumped elements (The transistor was biased at Vds = 3 V and Ids = 10 mA)
Efficient models are the key of successful designs. Widely used in modern wireless communication systems, active devices such as field-effect transistors (FETs) require up-to-date models to achieve reliable circuit/system design especially in terms of noise performance since most of communication systems operate in noisy environments. -. Among existing FET modeling techniques, the full-wave modeling approach can be considered as the most reliable but is computationally expensive in terms of CPU time and memory -. On the other side, circuit equivalent models are fast but cannot accurately integrate EM effects. Therefore, a hybrid transistor model, called the semi-distributed model (Sliced model) has been proposed . With the assumption of a quasi transverse electromagnetic (TEM) approximation, this model can be seen as a finite number of cascaded cells, each of them representing a unit transistor equivalent circuit. However, this model presents some limitations. In fact, in mm-wave frequencies, it cannot precisely take into account some EM effects that can significantly degrade the overall device behavior, like the wave propagation and the phase cancellation phenomena. To efficiently include such effects more general distributed models need to be developed. In this chapter, a new distributed FET model is proposed. In this model- , each infinitely unit segment of the device electrodes was divided into two parts namely, active and passive. The passive part describes the behavior of the transistor as a set of three coupled transmission lines while the active part that can be modeled by an electrical equivalent distributed circuit whose elements are all per-unit length.
To demonstrate the efficiency of our model in terms of noise, we applied the Laplace transformation to the device as an active multi-conductor transmission line structure and successfully compared its simulated response to measurements. Furthermore, by easily including the effects of scaling, the proposed algorithm is suitable for integration in computer-aided-design (CAD) packages for MMIC design.
2. Signal modeling of high-frequency FET
A typical millimeter-wave field effect transistor (FET) is shown in Fig.1. It consists on three coupled electrodes (i.e., three active transmission lines).
In the lower part of the microwave spectrum, the longitudinal electromagnetic (EM) field is very small in magnitude as compared to the transverse field -. Therefore, a quasi-TEM mode can be considered to obtain the generalized active multi-conductor transmission line equation. An equivalent circuit of a section of the transistor is shown in Fig. 2. Each segment is represented by a 6-port equivalent circuit which combines a conventional FET small-signal equivalent circuit model with a distributed circuit to account for the coupled transmission line effect of the electrode structure where the all parameters are per unit length. By applying Kirchhoff’s current laws to the left loop of the circuit in Fig. 2 with the condition Δx → 0, we obtain the following system of equations -:
where Vd, Vg, and Vs, are the drain, gate and source voltages, respectively, V’g is the voltage across gate-source capacitor, while Id, Ig, and Is are the drain, gate and source currents, respectively. These variables are time-dependant and function of the position x along the device width. Also, Mds, Mgd, and Mgs represent the mutual inductances between drain-source, gate-drain and gate-source, respectively; In the above system, we have an extra unknown parameter, i.e., the gate-source capacitance voltage Vg’. Therefore, the following equation should be included to complete the system of equations
which can be then reformatted into two matrix equations
3. Noise modeling of high-frequency FETs
The transmission line structure, exciting by noise equivalent sources distributed on the conductors as a new noise model of the high-frequency FET is shown in Fig. 3.
Applying Kirchhoff’s laws in time domain leads to
Note that vectors and are the linear density of exciting voltage and current noise sources, respectively. To evaluate the noise sources, we considered a noisy FET subsection with gate width, as shown in Fig. 4. Thus, the unit-per-length noise correlation matrix for chain representation of the transistor (CAUPL) can be deduced as
Where denotes the ensemble average and + the transposed complex conjugate. According to the correlation matrix definition, we can calculate and knowing (CAUPL), to completely describe the proposed FET noise model. Indeed, by solving (11), the noise parameters of the transistor can be obtained.
4. The FDTD formulation
The FDTD technique was used to solve the above equations. Applications of the FDTD method to the full-wave solution of Maxwell’s equations have shown that accuracy and stability of the solution can be achieved if the electric and magnetic field solution points are chosen to alternate in space and be separated by one-half the position discretization, e.g., Δx/2, and to also be interlaced in time and separated by Δt/2 . To incorporate these constraints into the FDTD solution of the transmission-line equations, we divided each line into Nx sections of length Δx, as shown in Fig. 5. Similarly, we divided the total solution time into segments of length Δt. In order to insure the stability of the discretization process and to insure second-order accuracy, we interlaced the Nx + 1 voltage points, V1, V2 … VNx+1 and the Nx current points, I1, 12... INx. Each voltage and adjacent current solution points were separated by Δx/2. In addition, the time points are also interlaced, and each voltage time point and adjacent current time point were separated by Δt/2. Then, (10) can lead to
Applying the finite difference approximation to (7) gives
and where k, m and n are integers. Solving these equations give the required recursion relations
Superposing all the distributed noise sources is equivalent to a summation in (20) and (21) over the gate width for m = 1…. Nx+1. Because of its simplicity, the leap-frog method was used to solve the above equations. First the voltages along the line were solved for a fixed time using (20) then the currents were determined using (21). The solution starts with an initially relaxed line having zero voltage and current .
5. Noise correlation matrix of transistor
To find the noise correlation matrix for admittance representation of the transistor as a noisy six-port active network (as in Fig. 2), the values of port currents should be determined when they are all assumed short-circuited simultaneously. Equation (20) for k = 0 and k = Nx +1 becomes
By considering Fig. 3, this equation requires that we replace Δx with Δx/2 only for k = 1 and k = Nx+1.
In order to determine the transistor noise parameters, we set the input voltage source as zero () - . Referring Fig. 6 we denoted the currents at the source point (x = 0) as I0 and at the load point (x = L) as INx+1. By substituting this notation into (22) we obtain
Similarly, we imposed the terminal constraint at x = L by substituting INx+1 into (23) as follow:
To determine the currents I1 and INx at short-circuited ports (x=0 and x=L), we set . The finite difference approximation of (21) for k = 1 and k = Nx can be then written as (26) and (27), respectively.
Finally, the currents of the short-circuited ports can be determined as
The admittance noise correlation matrix of the six-port FET noise model is then equal to
6. CAD algorithms for noise analysis of mm-wave FETs
6.1. Multi-port network connection
In Fig. 7, a noisy multiport sub-network S of scattering matrix [S] is embedded in a noisy sub-network T of scattering matrix [T], with respective noise wave correlation matrices noted [Cs] and [Ct]. Let [Snet] and [Cnet] be the scattering and noise wave correlation matrices of the total network called N. The scattering matrix [T] of the embedding network T can be partitioned into sub-matrices that satisfy
where subscript i designates the internal waves at the connections between the two-networks S and T while subscript e designates the external waves at the Snet terminals. The noise wave correlation matrix of network T is similarly partitioned such that
The resulting noise wave correlation matrix is then given by :
where [I] is the identity matrix and the connection matrix expressed as
The scattering matrix of the total network N is then given by the well known expression 
Note that this result gives a complete noise characterization of the network. A direct calculation of the new scattering matrix is now possible using (36). Note that the order of the matrix to be inverted was reduced by an amount equals to the number of the external ports.
6.2. Scattering and correlation noise matrices
According to the algorithm described above, let us consider the network shown in Fig. 8. In this figure, the ports of the transistor model are numbered from 1 to 24. Ports 23 and 24 are external ports while the rest are internal ports. Since most of the FETs are symmetrical, we can split their geometry into two identical parts. Figure 5 can be then decomposed into two equal parts of w/2 each (where w is the gate width) of respective scattering matrix [S(1)] and [S(2)]. Ports 13, 14 and 15 (the drain, the gate and the source) are terminated by the respective impedances Zd, Zg, and Zs, whose reflection coefficients can be expressed as
Let us now consider open circuit ports at x = w/2. We have then,
The only remaining components in Fig. 8 are the 3-port elements S (9) and S (10). Referring to that figure, we can observe that these components basically form the gate line and the drain line, respectively, in the transmission line model. Based on , their scattering matrix can be written as
In order to define, we need to know the noise correlation matrices in the form of scattering matrices for all circuit elements. The correlation noise matrix for the 6-port network representing half of the transistor gate width, i.e., w/2, can be computed using the techniques described in  and . As a result, we can use the proposed CAD algorithm to obtain the scattering and noise correlation matrices of the half-circuit structure.
The scattering matrix of a device is usually computed by partitioning its ports into two groups namely, external and internal ports. Thus, by separating the incoming and outgoing waves in (34), the computation of the connection matrix leads to the resulting scattering matrix
Then,  can be written as
Note that based on the proposed algorithm, a designer can easily obtain the scattering matrices of any microwave transistor, highlighting the ease of implementation of the proposed model into existing commercial simulators.
7. Numerical results
The proposed approach was used to model a sub micrometer-gate GaAs transistor (NE710) . The device has a 0.3 μm × 280 μm gate. The first step consisted to characterize the transistor. In this work, we used a bench from Focus microwave that consists on a probing station, the HP 8340B synthesized signal generator, the Agilent 8565EC spectrum analyzer, the CMMT1808 tuners, the Anritsu ML2438A power meter, and the Agilent ML2438A power supplies (Fig. 10).
The intrinsic equivalent circuit model (Fig. 11) was obtained using well-known hot and cold modeling techniques . After removing the extrinsic components via de-embedding methods, a hot modeling technique was utilized to obtain the intrinsic elements. Then, an optimization was performed by varying the values of the intrinsic FET elements in the vicinity of 10% of their mean value until the error between measured and modeled S-parameters was found acceptable (i.e., less than 2%). The obtained values of the extrinsic and intrinsic elements are summarized in Table 1.
Figure 12 shows a good fitting between measured and modeled data for various dc and pulsed voltages while Fig.13 shows the experimental load-pull characteristics of the transistor. When matched, it has an output power of 16 dBm with a 10% PAE at 10GHz. In Fig.10, the output RF power is shown as a function of the complex output impedance matching conditions of the device. The transistor S-parameters over a frequency range of 1-26GHz are plotted in Fig.14. As expected, compared to measurements, our proposed model is more accurate than the slice model , especially at the upper part of the frequency spectrum, when the device physical dimensions are comparable to the wavelength. This is due to the fact that our model is based on the full-wave equation while the slice model is based on an electrical equivalent circuit model. Figure 15 shows the noise figure obtained for three different frequencies. Thus, the proposed wave analysis can be applied for accurate noise analysis of FET circuits. To further prove the accuracy of the proposed wave approach in noise analysis, our results were successfully compared to measurements (Fig. 16).
For larger widths, the thermal noise of the gate increases due to the higher gate resistance while for smaller gate widths, the minimum noise figure increases as the capacitances do not scale proportionally with the gate width due to an offset in capacitance at gate width zero . Therefore, we highlighted these effects of gate width on a transistor noise performance by simulating the minimum noise figure and the normalized equivalent noise admittance for three values of the gate width, e.g., 140, 280 and 560 µm (Fig. 17). These values were selected based on the device we modeled. In fact, the NE710 has a gate width of 280 μm, so we took half of that value as well as its double to bound the device behavior and highlight the effect of gate width on a FET performance.
|Lumped Model Values||Numerical Values|
The transistor modeling approach presented in this chapter is mainly developed for computer-aided design implementation, making it suitable for any FET circuit topology up to the millimeter-wave range and thus, can be easily implemented and used in commercial software. As illustrated in Fig.18, the proposed model was implemented in ADS  and the results obtained from the code we developed have been successfully compared with those obtained by the same model after being implemented in the ADS library and used as an internal device. This step shows that the proposed model can be used in any microwave integrated circuit design performed by a commercial simulator. It has also to be noted that even if the proposed model is suitable for any FET structure, large-gate width devices have been targeted in the present work. In fact, this specific type of transistors can handle high output power levels, making them suitable for power amplifier design.
Using a new CAD algorithm, the noise modeling and analysis of microwave FET have efficiently been studied. In fact, since only half of a FET length is used, instead of the whole structure, the computation time will be significantly affected. Besides, the implementation of this CAD technique in modern microwave and mm-wave simulators is straightforward and will give more reliable results for circuit performance like low-noise amplifiers. Also, as for practical applications, large gate periphery devices are used to generate sufficient output power levels. With the increase of the device gate periphery, the self-heating effect and the defect trapping effect will both be more profound.