Open access peer-reviewed chapter

Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology

By Kittipong Tripetch

Submitted: November 23rd 2016Reviewed: December 15th 2017Published: February 28th 2018

DOI: 10.5772/intechopen.73157

Downloaded: 324

Abstract

Analog notch filters schematics are very rare. Two circuit diagrams are reviewed with symbolic equations. The first schematic is analog notch filter based on twin-T circuit diagram. The second schematic is analog notch filter based on the Friend biquad circuit.

Keywords

  • analog notch filter
  • high-order filter
  • LCR prototype
  • interference rejection

1. Introduction

Notch filters or band stop filters have many types of applications. The first application is interference mitigation in GNSS receiver [1]. The second application is the removal of powerline noise from biomedical signals which have operating frequency range from 50 to 60 Hz, while biomedical signal such as EEG has magnitude response in the range of 1–40 Hz [2]. The third application is for a radio frequency image rejection [3]. The fourth application is for an interference rejection in UWB systems. In this application, the filter can notch the magnitude more than 35 db at operating frequency of 900 MHz [4].

A second-order notch can be constructed using an LCR passive prototype. The advent of the very large-scale integration allows tens of thousands of transistors to be fabricated in an integrated circuit. CMOS analog notch filters can be easily designed and built in an IC chip. There are many types of techniques to design analog filter at the architecture or block diagram level such as active RC filter, Gm-C filter, switched Capacitor filter, etc. In this chapter, we will design analog notch filter based on Gm-C filter block diagram.

2. Transconductor capacitor filter based on floating active inductors

There are many choices of transconductor in the literatures. The first transconductor was published by Nedungadi [5]. It is proposed since 1984. This transconductor is very linear; its linear range can be extended by design and simulation. The circuit diagram is shown in Figure 1 . Its typical linear range, which is output current versus input voltage, can be plotted by level 1 transistor model as follows.

Figure 1.

(a) Differential amplifier with cross couple concept, (b) replacement of ideal voltage source with transistor in (a), and (c) cross couple circuit diagram with cascade active load.

Drain current of an NMOS and a PMOS transistor can be expressed as follows [6]:

ID=μnCox2WLVGSVTH21+λVDSE1
ID=μpCox2WLVGSVTH21λVDSE2

where IDis the drain current, μnis the electron mobility, μpis the hole mobility, Coxis oxide thickness and λis the channel length modulation.

For submicron CMOS, drain current of NMOS and PMOS transistor can be shown in the formulas (3) and (4). As a consequence of high electric field, both x and y dimensions are a derivative of electric filed by distance along x- and y-axes:

ID=WLμeCox1+VDSECLVGSVTHVDS2VDSμe=μ01+VGSVTHθtoxη,η=1.85for0.13μmE3
IDS=WvsatCoxVGSVTH2VGSVTH+ECLWvsatCoxVGSVTHECLVGSVTHfor long channel deviceECLVGSVTHforshort channel deviceE4

In order for someone to plot linear range by using multiple transistors, output current can be written as a function input voltage by writing KVL around the loop. Another way of representation is to derive small signal transconductance gain in frequency domain which is a ratio of output current which flows out from the output node divided by input voltage. Small-signal equivalent circuit concept can make the circuit analysis difficult because of parasitic capacitance. Transconductor circuit diagram which has too many transistors may not work if it is believed in small-signal circuit concept because the circuit has too many poles and zeros which make the element substitution of transconductor to deviate from ideal transfer function of LCR prototype.

3. Second-order notch filter

Circuit idea of notch filter is very rare. This is because the theory of an ideal second-order transfer function is well defined. The notch filter or band reject filer is found to be expressed as (5) below [7]:

Hs=s2+ωz2s2+ωpQps+ωp2E5

where ωzis the notch frequency, ωpis a pole frequency and ωz=ωp.

Numerator polynomial can be designed to have any value so that the roots of the numerator polynomial have roots of it equal with complex zero after equating them with zero.

The circuit which implements this function is called twin-T RC network which can be drawn in Figures 2 and 3 .

Figure 2.

(a) Twin T network and (b) twin T network with buffered op-amp.

Figure 3.

The Friend Biquad circuit.

A. Appendix

The notch filter block diagram is analyzed with Kirchoff current law to prove that it is notch filter transfer function. There are two notch circuits in this appendix. The passive element has its own name without any duplication of names. The current is assumed to flow from left to right and flow from positive potential to ground. Also assume that all nodes in the circuit have positive potential except ground node.

VinV1R1=V1R3+V1VoutsC1E6
VinV2sC2=V2sC3+V2VoutR2E7
V1VoutsC1+V2VoutR2=Vout1R4+sC4E8
VinV1R1=V1R3+V1VoutsC1VinV1sC1R3=V1sC1R1+V1VoutR1R3VinsC1R3=V1sC1R1+sC1R3+R1R3VoutR1R3E9
VinV2sC2=V2sC3+V2VoutR2VinV2sC3R2=V2sC2R2+V2Vouts2C2C3VinsC3R2=V2sC3R2+sC2R2+s2C2C3Vouts2C2C3V2=VinsC3R2+Vouts2C2C3sC3R2+sC2R2+s2C2C3E10
V1VoutsC1+V2VoutR2=Vout1R4+sC4=Vout1+sC4R4R4V1VoutR2R4+V2VoutsC1R4=Vout1+sC4R4sC1R2V1R2R4+V2sC1R4=VoutsC1R2+s2C4R4C1R2+R2R4+sC1R4V1=Vouts2C4R4C1R2+sC1R2+C1R4+R2R4V2sC1R4R2R4=Vouts2a21+sa11+a01V2sC1R4R2R4E11

Substitute Eq. (11) into an Eq. (9):

VinV1R1=V1R3+V1VoutsC1VinV1sC1R3=V1sC1R1+V1VoutR1R3VinsC1R3=V1sC1R1+sC1R3+R1R3VoutR1R3VinsC1R3=Vouts2a21+sa11+a01V2sC1R4R2R4sC1R1+sC1R3+R1R3VoutR1R3VinsC1R3R2R4=Vouts2a21+sa11+a01V2sC1R4sC1R1+sC1R3+R1R3VoutR1R3R2R4Vinsa12=Vouts2a21+sa11+a01sC1R1+sC1R3+R1R3R1R3R2R4V2sC1R4sC1R1+C1R3+R1R3E12

Substitute an Eq. (10) into an Eq. (12):

Vinsa12=Vouts2a21+sa11+a01sC1R1+sC1R3+R1R3R1R3R2R4V2sC1R4sC1R1+C1R3+R1R3Vinsa12=Vouts2a21+sa11+a01sC1R1+sC1R3+R1R3R1R3R2R4VinsC3R2+Vouts2C2C3sC3R2+sC2R2+s2C2C3sC1R4sC1R1+C1R3+R1R3Vinsa12sC3R2+C2R2+s2C2C3=Vout[s2a21+sa11+a01sC1R1+sC1R3+R1R3R1R3R2R4]sC3R2+sC2R2+s2C2C3VinsC3R2+Vouts2C2C3sC1R4sC1R1+C1R3+R1R3E13
Vinsa12sC3R2+C2R2+s2C2C3=Vouts2a21+sa11+a01sC1R1+C1R3+R1R3R1R3R2R4sC3R2+C2R2+s2C2C3VinsC3R2+Vouts2C2C3sC1R4sC1R1+C1R3+R1R3Vins3a12C2C3+s2a12C3R2+C2R2=Vouts3a21C1R1+sC1R3+s2a21R1R3R1R3R2R4+a11C1R1+C1R3+sa11R1R3R1R3R2R4+a01C1R1+C1R3+a01R1R3R1R3R2R4sC3R2+C2R2+s2C2C3Vins3C3R2C1R4C1R1+C1R3+sC3R2R1R3Vouts3C2C3C1R4C1R1+C1R3+s2C2C3R1R3E14
Vins3a12C2C3+s2a12C3R2+C2R2=Vouts3a33+s2a23+sa13+a03sC3R2+C2R2+s2C2C3Vins3C3R2C1R4C1R1+C1R3+sC3R2R1R3Vouts3C2C3C1R4C1R1+C1R3+s2C2C3R1R3a33=a21C1R1+sC1R3,a23=a21R1R3R1R3R2R4+a11C1R1+C1R3,a13=a11R1R3R1R3R2R4+a01C1R1+C1R3a03=a01R1R3R1R3R2R4Vins3a12C2C3+C3R2C1R4C1R1+C1R3+s2a12C3R2+C2R2+sC3R2R1R3=Vouts3a33+s2a23+sa13+a03sC3R2+C2R2+s2C2C3Vouts3C2C3C1R4C1R1+C1R3+s2C2C3R1R3a34=a12C2C3+C3R2C1R4C1R1+C1R3,a24=a12C3R2+C2R2,a14=C3R2R1R3E15
Vins3a34+s2a24+sa14=Vouts3a33+s2a23+sa13+a03sC3R2+C2R2+s2C2C3Vouts3a35+s2a25a34=a12C2C3+C3R2C1R4C1R1+C1R3,a24=a12C3R2+C2R2,a14=C3R2R1R3a35=C2C3C1R4C1R1+C1R3,a25=C2C3R1R3Vins3a34+s2a24+sa14=Vouts5a33C2C3+s4a23C2C3+a33C3R2+C2R2+s3a23C3R2+C2R2+a13C3R2+C2R2a35+s2a13C3R2+C2R2+a03C2C3a25sa03C3R2+C2R2VoutVin=s3a34+s2a24+sa14s5a33C2C3+s4a23C2C3+a33C3R2+C2R2+s3a23C3R2+C2R2+a13C3R2+C2R2a35+s2a13C3R2+C2R2+a03C2C3a25sa03C3R2+C2R2=ss2a34+sa24+a14ss4a33C2C3+s3a23C2C3+a33C3R2+C2R2+s2a23C3R2+C2R2+a13C3R2+C2R2a35+sa13C3R2+C2R2+a03C2C3a25+a03C3R2+C2R2E16

KCL at V 1:

VinV1R1=V1V4sC1+V1V2sC2VinV1=V1sC1R1+sC2R1V2sC2R1V4sC1R1Vin=V1sC1R1+sC2R1+1V2sC2R1V4sC1R1VinV1x1+V2x2+V4x3=0x1=sC1R1+sC2R1+1x2=sC2R1x3=sC1R1E17

KCL at V 2:

V1V2sC2=V2V4R3+V2R4V1sC2=V2sC2+1R3+1R4V41R3V1sC2V2x4+V4x5=0x4=sC2+1R3+1R4x5=1R3E18

KCL at V 3:

VinV3R2=V3R5+V3V4R6VinR2=V31R2+1R5+1R6V41R6Vinx6V3x7+V4x8=0x6=1R2x7=1R2+1R5+1R6x8=1R6E19

KCL at V 4:

V3V4R6+VoutV4R7=V4R8V3R6V41R6+1R7+1R8+VoutR7=0V3x9V4x10+Voutx11=0x9=1R6x10=1R6+1R7+1R8x11=1R7E20

KCL at Vout :

AvV3V2=VoutV4R7V2Av+V3Av+V4R7VoutR7=0V2Av+V3Av+x12V4x12Vout=0x12=1R7E21

All of these equations can be written in matrix form as follows:

1x1x20x300sC2x40x50x600x7x80000x9x10x1100AvAvx12x12VinV1V2V3V4Vout=000000E22

From Eq. (17), it can be rewritten as follows:

VinV1x1+V2x2+V4x3=0Vin=V1x1V2x2V4x3E23

Substitute Eq. (23) into Eq. (19); we will get the following equation:

Vin=V1x1V2x2V4x3Vinx6V3x7+V4x8=0V1x1V2x2V4x3x6V3x7+V4x8=0V1x1x6V2x2x6V3x7+V4x8x3x6=0V1y1V2y2V3x7+V4y3=0y1=x1x6=sC1R1+C2R1+1R2y2=x2x6=sC2R1R2y3=x8x3x6=1R6sC1R1R2=R2sC1R1R6R6R2E24

All of these equations can be written in matrix form as follows:

1x1x20x300sC2x40x500y1y2x7y30000x9x10x1100AvAvx12x12000000VinV1V2V3V4Vout=000000E25

From Eq. (24), it can be rewritten as follows:

V1y1V2y2V3x7+V4y3=0V1=V2y2+V3x7V4y3y1E26

Substitute Eq. (26) into Eq. (17); we will get the following equation:

V1=V2y2+V3x7V4y3y1VinV1x1+V2x2+V4x3=0VinV2y2+V3x7V4y3y1x1+V2x2+V4x3=0Vin+V2x2y2x1y1V3x7x1y1+V4x3y3x1y1=0Vin+V2y4V3y5+V4y6=0y4=x2y2x1y1=sC2R1sC2R1R2sC1R1+C2R1+1sC1R1+C2R1+1R2=0y5=x7x1y1=1R2+1R5+1R6sC1R1+C2R1+1sC1R1+C2R1+1R2=R2R2+R2R5+R2R6y6=x3y3x1y1=sC1R1R2sC1R1R6R6R2sC1R1+C2R1+1R2sC1R1+C2R1+1=sC1R1R2sC1R1R6R6=s2C1R1R2R6E27

All of these equations can be written in matrix form as follows:

10y4y5y600sC2x40x500y1y2x7y30000x9x10x1100AvAvx12x12000000VinV1V2V3V4Vout=000000E28

From Eq. (18), it can be rewritten as follows:

V1sC2V2x4+V4x5=0V1=V2x4V4x5sC2E29

Substitute Eq. (29) into Eq. (24); we will get the following equation:

V1=V2x4V4x5sC2V1y1V2y2V3x7+V4y3=0V2x4V4x5sC2y1V2y2V3x7+V4y3=0V2x4y1sC2y2V3x7+V4y3x5y1sC2=0V2y7V3x7+V4y8=0y7=x4y1sC2y2=sC2+1R3+1R4sC1R1+C2R1+1sC2R2sC2R1R2y7=sC2+1R3+1R4sC1R1+C2R1+1sC2R1sC2sC2R2=s2C2C1R1+sC2+1R3+1R4C1R1+C2R1+1R3+1R4sC2R2y8=y3x5y1sC2=R2sC1R1R6R6R21sC2R3sC1R1+C2R1+1R2=R2sC1R1R6sC2R3R6sC1R1+C2R1+1sC2R2R3R6y8=s2C1R1R6C2R3+sR2C2R3R6C1R1R6C2R1R6sC2R2R3R6E30

All of these equations can be written in matrix form as follows:

10y4y5y600sC2x40x5000y7x7y80000x9x10x1100AvAvx12x12000000VinV1V2V3V4Vout=000000E31

From Eq. (30), it can be rewritten as follows:

V2y7V3x7+V4y8=0V2=V3x7V4y8y7E32

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (27):

V2=V3x7V4y8y7Vin+V2y4V3y5+V4y6=0Vin+V3x7V4y8y7y4V3y5+V4y6=0Vin+V3x7y4y7y5+V4y6y8y4y7=0Vin+V3y9+V4y10=0y9=x7y4y7y5y10=y6y8y4y7E33

Update matrix in Eq. (31) by substituting Eq. (33) into as follows:

100y9y1000sC2x40x5000y7x7y80000x9x10x1100AvAvx12x12000000VinV1V2V3V4Vout=000000E34

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (29):

V2=V3x7V4y8y7V1sC2V2x4+V4x5=0V1sC2V3x7V4y8y7x4+V4x5=0V1sC2V3x7x4y7+V4x5+y8x4y7=0V1sC2V3y11+V4y12=0E35

Update matrix in Eq. (34) by substituting Eq. (35) into as follows:

1.42.33.3100y9y1000sC20y11y12000y7x7y80000x9x10x1100AvAvx12x12VinV1V2V3V4Vout=000000E36

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (21):

V2=V3x7V4y8y7V2Av+V3Av+x12V4x12Vout=0V3x7V4y8y7Av+V3Av+x12V4x12Vout=0V3Avx7Avy7+V4x12+y8Avy7Voutx12=0V3z1+V4z2Voutx12=0E37

Update matrix in Eq. (34) by substituting Eq. (37) into as follows:

100y9y1000sC20y11y12000y7x7y80000x9x10x11000z1z2x12000000VinV1V2V3V4Vout=000000E38

From Eq. (20), it can be rewritten as follows:

V3x9V4x10+Voutx11=0V3=V4x10Voutx11x9E39

Substitute Eq. (39) into Eq. (37); we will get the following equation:

V3=V4x10Voutx11x9V3z1+V4z2Voutx12=0V4x10Voutx11x9z1+V4z2Voutx12=0V4x10z1x9+z2Voutx11z1x9+x12=0V4z3Voutz4=0E40

Update matrix in Eq. (36) by substituting Eq. (40) into as follows:

100y9y1000sC20y11y12000y7x7y80000x9x10x110000z3z4000000VinV1V2V3V4Vout=000000E41

Substitute Eq. (39) into Eq. (30); we will get the following equation:

V3=V4x10Voutx11x9V2y7V3x7+V4y8=0V2y7V4x10Voutx11x9x7+V4y8=0V2y7+V4y8x10x7x9+Voutx11x7x9=0V2y7+V4z5+Voutz6=0E42

Update matrix in Eq. (41) by substituting Eq. (40) into as follows:

100y9y1000sC20y11y12000y70z5z6000x9x10x110000z3z4000000VinV1V2V3V4Vout=000000E43

Substitute Eq. (39) into Eq. (33); we will get the following equation:

V3=V4x10Voutx11x9Vin+V3y9+V4y10=0Vin+V4x10Voutx11x9y9+V4y10=0Vin+V4x10y9x9+y10Voutx11y9x9=0Vin+V4z7Voutz8=0E44

Update matrix in Eq. (43) by substituting Eq. (44) into as follows:

1000z7z80sC20y11y12000y70z5z6000x9x10x110000z3z4000000VinV1V2V3V4Vout=000000E45

Substitute Eq. (37) into Eq. (44); we will get the following equation:

V4z3Voutz4=0V4=Voutz4z3Vin+V4z7Voutz8=0Vin+Voutz4z3z7Voutz8=0Vin+Voutz4z7z3z8=0Vin+Voutz9=0VoutVin=1z9E46

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution 3.0 License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Kittipong Tripetch (February 28th 2018). Design of High-Order CMOS Analog Notch Filter with 0.18 μm CMOS Technology, Very-Large-Scale Integration, Kim Ho Yeap and Humaira Nisar, IntechOpen, DOI: 10.5772/intechopen.73157. Available from:

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