## Abstract

Analog notch filters schematics are very rare. Two circuit diagrams are reviewed with symbolic equations. The first schematic is analog notch filter based on twin-T circuit diagram. The second schematic is analog notch filter based on the Friend biquad circuit.

### Keywords

- analog notch filter
- high-order filter
- LCR prototype
- interference rejection

## 1. Introduction

Notch filters or band stop filters have many types of applications. The first application is interference mitigation in GNSS receiver [1]. The second application is the removal of powerline noise from biomedical signals which have operating frequency range from 50 to 60 Hz, while biomedical signal such as EEG has magnitude response in the range of 1–40 Hz [2]. The third application is for a radio frequency image rejection [3]. The fourth application is for an interference rejection in UWB systems. In this application, the filter can notch the magnitude more than 35 db at operating frequency of 900 MHz [4].

A second-order notch can be constructed using an LCR passive prototype. The advent of the very large-scale integration allows tens of thousands of transistors to be fabricated in an integrated circuit. CMOS analog notch filters can be easily designed and built in an IC chip. There are many types of techniques to design analog filter at the architecture or block diagram level such as active RC filter, Gm-C filter, switched Capacitor filter, etc. In this chapter, we will design analog notch filter based on Gm-C filter block diagram.

## 2. Transconductor capacitor filter based on floating active inductors

There are many choices of transconductor in the literatures. The first transconductor was published by Nedungadi [5]. It is proposed since 1984. This transconductor is very linear; its linear range can be extended by design and simulation. The circuit diagram is shown in Figure 1 . Its typical linear range, which is output current versus input voltage, can be plotted by level 1 transistor model as follows.

Drain current of an NMOS and a PMOS transistor can be expressed as follows [6]:

where

For submicron CMOS, drain current of NMOS and PMOS transistor can be shown in the formulas (3) and (4). As a consequence of high electric field, both x and y dimensions are a derivative of electric filed by distance along x- and y-axes:

In order for someone to plot linear range by using multiple transistors, output current can be written as a function input voltage by writing KVL around the loop. Another way of representation is to derive small signal transconductance gain in frequency domain which is a ratio of output current which flows out from the output node divided by input voltage. Small-signal equivalent circuit concept can make the circuit analysis difficult because of parasitic capacitance. Transconductor circuit diagram which has too many transistors may not work if it is believed in small-signal circuit concept because the circuit has too many poles and zeros which make the element substitution of transconductor to deviate from ideal transfer function of LCR prototype.

## 3. Second-order notch filter

Circuit idea of notch filter is very rare. This is because the theory of an ideal second-order transfer function is well defined. The notch filter or band reject filer is found to be expressed as (5) below [7]:

where

Numerator polynomial can be designed to have any value so that the roots of the numerator polynomial have roots of it equal with complex zero after equating them with zero.

The circuit which implements this function is called twin-T RC network which can be drawn in Figures 2 and 3 .

## A. Appendix

The notch filter block diagram is analyzed with Kirchoff current law to prove that it is notch filter transfer function. There are two notch circuits in this appendix. The passive element has its own name without any duplication of names. The current is assumed to flow from left to right and flow from positive potential to ground. Also assume that all nodes in the circuit have positive potential except ground node.

Substitute Eq. (11) into an Eq. (9):

Substitute an Eq. (10) into an Eq. (12):

KCL at *V* _{1}:

KCL at *V* _{2}:

KCL at *V* _{3}:

KCL at *V* _{4}:

KCL at *Vout *:

All of these equations can be written in matrix form as follows:

From Eq. (17), it can be rewritten as follows:

Substitute Eq. (23) into Eq. (19); we will get the following equation:

All of these equations can be written in matrix form as follows:

From Eq. (24), it can be rewritten as follows:

Substitute Eq. (26) into Eq. (17); we will get the following equation:

All of these equations can be written in matrix form as follows:

From Eq. (18), it can be rewritten as follows:

Substitute Eq. (29) into Eq. (24); we will get the following equation:

All of these equations can be written in matrix form as follows:

From Eq. (30), it can be rewritten as follows:

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (27):

Update matrix in Eq. (31) by substituting Eq. (33) into as follows:

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (29):

Update matrix in Eq. (34) by substituting Eq. (35) into as follows:

It is time to eliminate column 3 by Eq. (32) by substituting into Eq. (21):

Update matrix in Eq. (34) by substituting Eq. (37) into as follows:

From Eq. (20), it can be rewritten as follows:

Substitute Eq. (39) into Eq. (37); we will get the following equation:

Update matrix in Eq. (36) by substituting Eq. (40) into as follows:

Substitute Eq. (39) into Eq. (30); we will get the following equation:

Update matrix in Eq. (41) by substituting Eq. (40) into as follows:

Substitute Eq. (39) into Eq. (33); we will get the following equation:

Update matrix in Eq. (43) by substituting Eq. (44) into as follows:

Substitute Eq. (37) into Eq. (44); we will get the following equation: