## 1. Introduction

Limited voltage and current rating of semiconductors are the main limitations of the different static power converter topologies [1–4]. Diodes and thyristors are the power devices with the higher voltage blocking levels and conduction current levels, but diodes work with natural commutation while thyristors can only be communed to conduction condition. The above operation conditions do not allow one to control the electrical power transferred by the power converter—in diode‐based topologies—or have poor power quality, increasing not only the input harmonic but also injecting unwanted reactive power—thyristor‐based topologies - . On the other hand, force‐commuted power semiconductors allow controlling the electrical power transferred and increase the power quality in both input and output of the power converter. The device's voltage and current ratings are lower than diodes and thyristors, and so in order to reach higher voltage and current levels, the devices connection in series or in parallel are typically used. From this kind of connection, and gating the devices in a convenient way, it is possible to increase further the current and voltage quality, allowing reducing losses and the size of the filter components.

The cascaded H‐bridge (CHB) topologies are born under the next concept: to reach higher voltage levels using power valves with lower voltage rating, while a high power quality is keeping in the load and the power source [5–7]. Classical topology is based on H‐bridge voltage‐source inverters, where the series connection is natural because each inverter works as a controlled voltage source. Because of the series connection, each inverter can be disconnected from the whole array without this implying that the equipment should get offline, which is highly convenient when an inverter fails, increasing the reliability of the equipment. On the other hand, an array of nC cells per phase in a three‐phase system allows dividing the load power on 3nC cells [8] so that the electrical stress in each cell is lower than other power topologies as three‐phase inverters and their extension to multilevel topologies—as neutral point clamped, for example. A drawback of the cascaded connection is the power device losses which are mainly a function of the current level; in a cascaded connection, this current level is equal in all the power devices. On the other hand, for current‐source converter, the natural multilevel connection is using inverters in a parallel connection. This allows summing the current injected by each converter, increasing the current waveform capability. A drawback is that the voltage rating in all the semiconductors is equal to half of the load voltage, while the capacitive filter voltage rating is equal to the load voltage.

Cascaded H‐bridge based on current‐source inverter (CSI) is an emerging power topology that uses a current‐source inverter and a capacitive filter to synthetize a controlled voltage source that can be connected in series with other controlled voltage sources in order to reach higher voltage levels. It has been proposed for the first time in 2008 [9] for AC drive applications, and its study has been focused mainly in reducing the size of the DC inductor, the use of control techniques [10] and the compensation of using cells that are magnetically coupled [11–14], the control of the inverters using linear control and non‐linear control [15–17], and the modulation and design of the power topology [18, 19].

This chapter study the cascaded H‐bridge topology, without using any DC inductor reduction technique, focusing the study in operation of the power topology, the series connection of several current‐source inverters in series, the use of multilevel modulation techniques, and how it defines the size of the capacitive filter required for each inverter. Also, the effect of the oscillating power drained by the inverter is described, including how it defines the size of the DC inductor is studied. Finally, the application in an AC drive computing the operation region and the key waveform of the power topology for both steady states and step changes in the DC current are studied.

## 2. Power topology

### 2.1. Power cell based on single‐phase current‐source inverter

Each power cell based on a single‐phase current‐source inverter fed by an isolated DC current source is shown in **Figure 1**. In the single‐phase current‐source inverter, each power valve requires symmetric blocking capabilities in order to block the AC voltages which have positives or negative values. For the abovementioned requirement, power valves can be implemented using gate turn‐off thyristor (GTO) with insulated‐gate bipolar transistor (IGBT) with reverse blocking capability or an IGBT with a diode in series, in order to get the reverse blocking capability. Also, new semiconductor technologies such as wide bandgap semiconductors can be used, allowing increases in the switching frequency of the power converter.

In order to simplify the power cell analysis, let's assume that we can use an ideal DC current source. This DC current source fed the single‐phase inverter and, jointly, they injected a pulse width modulated current to the capacitor

then the current injected by the CSI and the voltage in the DC side are

and

The modulation function *s*_{i} can be approximated to its fundamental component; then,

and the injected current and the DC voltage

and

Using the above equations, the load voltage is equal to the capacitor voltage,

The simplification can be made only if

### 2.2. Modulation and harmonic compensation on CHB‐CSI

Because of the use of single‐phase current‐source inverter, two conditions must be avoided—(i) the electrical circuit of the DC current—typically based on an inductor—must not be open and (ii) the AC side must not be shortcircuited. The first case is because of the use of an inductor to synthetize the DC current source, and if it is open, the voltage on the power valves will theoretically become infinity; the second case is because the use of a capacitor is on the AC side. Then, if the capacitor is shortcircuited, the current on the semiconductor will be infinity. Both conditions can destroy the semiconductors used to implement the power valves.

Single‐phase current‐source inverter has four valid conditions (**Table 1**). Each state avoids the above conditions and allows transfer of electrical power to the load—state #1 and state #2—or disconnects the load from the DC current source—state #3 and state #4—also called zero states. On the other hand, on transitions between states—**Figure 2**—it is necessary to ensure that the electrical circuit of the current source is not open. For the above, an overlap must be implemented when the inverter state is changed. The overlap should last long enough for the power valve to complete the switch. In the example, the first state is #1 and final state is #4 and in the transition between the states, the overlap is implemented.

Because of the use of a capacitive filter in each power cell, CHB‐CSI topology is not a multilevel power topology but in the same way as that of multilevel topologies, the use of an appropriate modulation technique allows compensating some harmonics among inverters. In a typical current‐source multilevel topology, these harmonics will be harmonic currents; in a CHB‐CSI topology, the compensated harmonics will be voltage harmonics in the capacitive filter.

Sinusoidal pulse width modulation (SPWM) will be studied as an example of a modulation technique which can be used in CHB‐CSI topologies. SPWM has the following advantages: it is easy to implement using both analogic circuit and digital circuit, it has the facility to modify SPWM techniques to use it in a multilevel application and the fundamental gain of the modulation technique, which in single‐phase inverters, is unitary. In SPWM, a reference signal called modulator is compared with a triangular signal, also called carrier. Comparison generates a Boolean signal which is used to commutate the power valves. The inverters output signal is a pulse width modulated signal which has a wanted fundamental component and several unwanted harmonics which are the functions of the modulator frequency and the carrier fundamental frequency, so, higher carrier frequencies not only displace the unwanted harmonic to higher frequencies but also increase the commutations per period of the semiconductor devices. In multilevel topologies, the connection of the power converters in series—in the case of voltage‐source converters—or parallel—in the case of current‐source converters—allows to sum up the DC voltage/current levels and compensate the unwanted harmonics if they are generated and phase‐shifted among them in an appropriate way. In case of phase‐shifted carrier (PSC) sinusoidal pulse width modulation, the switching signals are generated comparing *n*_{C} carriers phase‐shifted at 180°/*n*_{C,} among them with a common modulator signal. An example simulated in MATLAB is shown in **Figure 3**. In the first case, the modulator signal is compared with the carrier, generating the pulse width modulation signal shown below (**Figure 3a**). Multilevel cases are **Figure 3b** and **Figure 3c** for *n*_{C} = 2 and *n*_{C} = 3, respectively, where the resulting waveform is of 5 levels for *n*_{C} = 2 and 7 levels for *n*_{C} = 3. Computing and comparing the total harmonic distortion (THD) of the three PWM signals presented, these values are 46, 25, and 14% for *n*_{C} = 1, *n*_{C} = 2, and *n*_{C} = 3, respectively, showing the reduction of the distortion of the resulting pulse width modulated waveform without increasing the commutation frequency. The above is valid for multilevel topologies. The effects of using PSC SPWM in a CHB‐CSI topology—which is not a multilevel topology—will be analyzed in the next section.

### 2.3. Cascaded connection of single‐phase CSI

Inverters with their isolated and controlled DC current source and their capacitive filter can be connected in a series array because each power cell is working as a controlled AC voltage source (**Figure 4**). With the above, the voltage of the array is the sum of all power cells connected to it, allowing (i) to use components with lower voltage ratings than the voltage of the application and (ii) to divide the power of the application in multiple power cells. **Figure 4** shows multiple power cells—which will be named as 3*n*_{C}—feeding a common three‐phase load. Each cell injects a controlled current to the load. Defining *j* phase, then

while the load voltage is the summation of the cell output voltage, each one is given by the voltage on the capacitor filter so

From the equations, it is clear that the connection of single‐phase inverters in a cascaded array allows dividing the load voltage *in N* cells, allowing the use of a semiconductor with lower voltage rating than the required load voltage, but the current in each cell is equal to the other, increasing semiconductor losses.

An advantage of the topology is the quality of the voltage waveform at the load. Because of the use of a capacitive filter, the sum of all cell output voltages is not a multilevel voltage, but through the multilevel modulation technique that is used in each inverter connected in series, it is possible to compensate the dominant harmonic among cells. An example of the above is shown in **Figure 5**, where the topology has been simulated using PSIM in order to obtain the load voltage waveform for *n*_{C} = 1, *n*_{C} = 2, and *n*_{C} = 3. For *n*_{C}= 2 and *n*_{C}= 3, a multilevel modulation technique—specifically phase‐shifted carried pulse width modulation—is used. For *n*_{C} = 1, one has THD = 28.2% which is reduced to THD = 9.6% in *n*_{C} = 3. The above is because dominant harmonic presented in each capacitor is phase shifted with the dominant harmonic in the other capacitor. Each capacitor voltage for N = 2 and *n*_{C} = 3 can be seen in **Figure 5d** and **e**, where each waveform is similar to the voltage capacitor in *n*_{C} = 1.

### 2.4. Isolated DC current source for power cells

Each power cell requires an isolated DC current source and there are several options to implement the DC current source. For example, a controlled rectifier in series with a DC reactor can be used to get, from the viewpoint of the inverter, a controlled DC current source. In order to isolate this DC current source from other DC current sources that feed other power cells, a power transformer is required. With the above, the rectifier stage can be implemented using single‐phase or three‐phase controlled rectifiers based on thyristor or force‐commuted semiconductors as IGBT or silicon carbide (SiC). Both cases require a DC reactor on the DC side; in thyristor rectifier cases, it can be connected directly to the secondary transformer while in force‐commuted semiconductor rectifiers, an LC filter is required between the secondary transformer and the rectifier. Another option is to use a diode rectifier and a DC/DC converter on the DC stage. This case limits the power that can be transferred to the inverter stage but is a good option for non‐conventional renewable power source. Also, if the source is a DC power source type, a DC/DC to regulate the DC current to the inverter stage can be used. This is the case of photovoltaic arrays and fuel cells. A third case is when the inverters are directly connected to the power grid. In this case, the DC current source can be implemented with the single‐phase inverter and the DC inductor. The DC current regulation must be implemented in the inverter control scheme.

## 3. DC Reactor on cascaded H‐bridge based on current source inverters

### 3.1. Oscillating power on single‐phase current‐source inverter

Using single‐phase inverters involving the occurrence of an oscillating and continuous power, it can be described as

where *M*_{i} is the inverter modulation index—considering fixed for this case—and *Z*_{m} is the equivalent impedance of the load in parallel with the inverter output capacitor as is shown in **Figure 6**. Then, the power drained from the cell can be written in terms of the cell energy, and the charge and discharge of the DC inductor current is

where *i*_{dc}(*t*_{1}) = *I*_{dc} e*i*_{dc}(*t*_{2}) = *I*_{dc}*k*_{dc}, and a *k*_{dc} near to 1 means that there is no variation in the DC current level. With the above, one can write

Then, the DC current variation, in per unit, can be written as

Considering that the power converter that feeds the DC inductor and the single‐phase inverter only injects to the DC side, the continuous power drained by the inverter—corresponding to the active power delivered by the inverter to the load—and that the voltage imposed by power converter in the DC side has mainly a DC component, another element must provide the oscillating power so that it does not disturb the DC current.

The easier solution to avoid the DC current variation due to the oscillating power is to increase the size DC inductor. This increases the losses in the DC link, along with the size of the inductor and increases the cost of each cell. Other options consider the use of active compensators in the DC side, tuned passive filters, or neutral leg. Specifically, for the case of an AC drive, the active compensation adds complexity to the topology, adding semiconductors and additional accumulators to DC link, besides requiring additional controllers to manipulate the semiconductors incorporated, but it is a good option when the inverters are directly connected to the electrical grid or when the CHB‐CSI topology is used in photovoltaics application. On the other hand, the passive techniques are mainly applied to cases where the frequency inverter is fixed, making a complex application for AC drives.

### 3.2. DC inductor design

The main objective of the DC inductor is to limit the DC current variation. Due to the oscillating power drained by the single‐phase inverter and its effects on the load current and load voltage, the lower frequency that the DC inductor must limit to is the second harmonic of the inverter frequency. Then, using Eq. (11) and defining *k*_{dc} in Eq. (13), the DC inductor can be computed with

## 4. Capacitive filter

### 4.1. Capacitive filter design as a function of the load voltage THD, *n*_{C} = 1

For *n*_{C} = 1, the inverter output voltage *v*_{o} is equal to the load voltage. Also, the output voltage total harmonic distortion is given by

where fundamental output voltage is defined by

with *M*_{i} as the modulation index and

On the other hand, output voltage harmonics are defined by the inverter current harmonics that flow through the capacitor. Then

Hence, Eq. (15) can be written as

Eq. (19) shows that the output voltage THD is a function of the filter reactance, impedance *Z*_{m}, and modulation techniques, including the modulation index. Grouping the terms defined by the modulation technique, *F*_{iac} can be defined as

Considering Eq. (17) on Eq. (15) and solving for *C*_{o}, it can be found that

where two solutions for C_{o} can be computed due to the ± sign in the denominator.

### 4.2. Capacitive filter design for *n*_{C} inverters

The fundamental load voltage is the summation of each capacitor's fundamental voltage (Eq. (9)) and this voltage will not change for

where the terms by the modulation technique can be summarized in one term defined by

Finally, *C*_{o} can be found solving Eqs. (22) and (23) for an RL load as shown in Eq. (24). Then, with *n*_{C} inverters in a cascaded device, *n*_{C} capacitors are needed, one for each inverter, and they can be computed using

Due to the series connection of the current‐source inverters, it is not possible to sum up the current level and obtain a multilevel current waveform—multilevel current source topologies must be connected in a parallel array to sum up currents levels, but it is possible to compensate voltage harmonic among the capacitor voltage. These harmonics are generated by the current harmonic injected by the inverters and are a function of the switching function—see Eq. (22)—therefore, if a multilevel modulation technique is used with the aim of generating current harmonics that are phase shifted, the DC current level in each inverter is the same and all outputs filters have the same capacitor value; some capacitor voltage harmonics will be phase shifted and can be compensated among cells. The amplitude of the voltage harmonic in each cell is a function of the capacitor value—see Eqs. (21) and (24)—so by increasing the capacitor size, the voltage harmonic will be increased and, at the same time, the capacitor voltage rating.

As examples, values of *F*_{iac} and *F*_{iacM} are computed for PSC‐SPWM using MATLAB and they are presented in **Figure 7**, considering modulation indexes 0.5 ≤ *M*_{i} ≤ 1 and different carrier frequencies for each case. For *F*_{iacM} is equal to *n*_{C} times *F*_{iac}. For example, a CHB‐CSI with a unitary modulation index (*M*_{i} = 1), three cells per phase (*n*_{C}= 3), and a 6 p.u. carrier frequency (*F*_{iacM} ≈ 0.038) shows *F*_{iacM} ≈ 0.114.

## 5. AC drive application

### 5.1. Description

An example of the use of the CHB‐CSI topology is AC Drive, where the power converter is connected in series to each phase of an electrical AC machine. In this case, a three‐phase machine is fed by *n*_{C} cells by phase, so the AC drive has 3*n*_{C} cells as is shown in **Figure 8**. For this example, each cell is fed by a three‐phase rectifier based on a current‐source rectifier which is connected to the AC grid through a power transformer. This power transformer typically is a multistep transformer in classical CHB‐CSI topology but can be simplified when active front ends are used, as in this case. Due to the use of a current‐source rectifier, an LC filter is required at the cell input stage.

In the same way, the multicell topology is based on voltage‐source inverters; the multicell topology based on current‐source inverters is designed to increase the load voltage, which is the sum of the voltage on each cell. Due to the series connection, the current in each cell is the same. Then, the fundamental load current shown in **Figure 8** is given by

The load voltage can be written in terms of the fundamental load current; thus,

For the transformer input current, if there is not a phase shift between the primary and the secondary, one can write

and the cell input voltage is defined as

Every cell is built up by a current source active front end which feeds a single‐phase inverter through the DC link inductor. In order to obtain several controlled voltage sources connected in series array to the load, single‐phase inverters and their respective capacitors are connected in series, achieving with this that each inverter‐capacitor set behaves like a voltage source controlled through their DC currents. Then, each cell, as is shown in **Figure 9**, can be modeled in *dq* axis; thus

where

with *dq* model, it is possible to define a control strategy for the rectifier stage. A control scheme must ensure the regulation of the DC current level in each cell (see **Figure 10**), allowing the use of a fixed modulation pattern in the inverter stage. The control scheme controls the active and reactive power using the currents at the input of the cell. An active power controller is used to control the DC current and, through the DC current, the cell output voltage, using the DC component of the output power of the cell. A reactive power controller can be used to compensate the reactive power of the LC filter. The control is replicated in each cell and the references of the output voltage, frequency, and cell reactive power are common to those controllers.

On the other hand, *dq* model allows to calculate the operation region of the topology and defines the active power _{C}, the LC filter, the modulation at the rectifier stage, and the transformer voltage and its ratio; so

where *P*_{c} and *Q*_{c} are the active power and reactive power in each power cell,

While the load voltage can be defined as

and

from Eqs. (34) and (35), it is possible to notice that for a required active power on the load (

### 5.2. Examples

In order to show the performance of the CHB‐CSI topology, an AC Drive is simulated using PSIM with the parameters shown in **Table 2**, considering a 9.33 MVA load per phase and a 0.8 inductive power factor, using one cell per phase (

**Figure 11** shows the operating region for **Figure 11a**) and load voltage and inverter voltage per cell (**Figure 11b**), where the RMS cell input voltage for

In terms of steady‐state performance, **Figure 12** shows the key waveform **Figure 12a**) and a load frequency equal to 50 Hz. For this case, unitary displacement power factor at the input of the power converter has been set in order to get input current in phase with the input voltage. It is possible to notice that, for the same DC inductor parameters, the ripple by the oscillating power is lesser in **Figure 12b** shows that both cases reach similar voltage levels, but the harmonic distortion in **Figure 12c** and **d** shows voltage and current for both cases, where one can see the low distortion in the input current—typically in current‐source rectifier topologies.

**Figure 13** shows the frequency spectra for the DC current (**Figure 13a**), load voltage (**Figure 13b**), and cell input current (**Figure 13c**). From the DC current frequency spectra, a second harmonic can be noticed due to the oscillating power drained by the single‐phase inverter limited by the DC inductor design. This component is lesser in the

Finally, for **Figures 14** and **15**, respectively). For these tests, a non‐linear control has been implemented in order to control the load voltage using the DC current level, which is controlled by the rectifier stage. In the first case, under frequency changes from 20 to 70 Hz (**Figure 14b**), the power topology is able to impose it on the load. For lower frequencies, the amplitude of the second harmonic in the DC current increases because the DC inductor has been designed to limit it at 50 Hz (**Figure 14a**) and decreases for higher frequencies. On the other hand, at the input current (**Figure 14c**), it is possible to notice the effect of the second harmonic in the DC current. This oscillation is not presented in the current at the primary transformer because of the compensation of these components among cells that feed different load phases.

About the DC current step change, **Figure 15a** shows a 10% step in t = 100 ms. In both cases, it can be notice that the load voltage increases by 10% (**Figure 15b**), while the input current increases in the same rate due the increases in the load power (**Figure 15c**). In this case, the dynamic is defined by the controller parameters and can be specified in the controller design process.

## 6. Conclusions

Cascaded H‐bridge topologies based on CHB‐CSI are emerging topologies that use the same principle of a cascaded H‐bridge converter, allowing to divide the required load voltage level and power into several single‐phase inverters connected in series. Advantages of the proposed topology are (i) high quality of voltage and current waveforms using lower switching frequencies and (ii) inherent short‐circuit protection because of the use of current‐source inverter, while its main drawbacks are (i) the use of a bulky DC inductor because of the use of current‐source inverters and (ii) the oscillating power drained by the inverter on the DC side, because the use of single‐phase inverters. With an appropriate control scheme, the CHB‐CSI is able to impose a desire frequency and load voltage level. In case of AC drive applications, an increase in the number of cells allows reducing the voltage rating of the components without reducing the operation region of the whole converter. At the same time, the DC current variation in each cell decreases when the number of cells increases. On the other hand, load voltage can be regulated through the DC current control, allowing the use of a fixed modulation index for the inverter stage. The above allows designing the capacitive filter with the minimum *F*_{iacM} required for a given modulation technique and switching frequency.