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Fast Algorithm Designs of Multiple-Mode Discrete Integer Transforms with Cost-Effective and Hardware-Sharing Architectures for Multistandard Video Coding Applications
Written By
Chih-Peng Fan
Submitted: 09 March 2016Reviewed: 21 July 2016Published: 23 November 2016
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In this chapter, first we give a brief view of transform-based video coding. Second, the basic matrix decomposition scheme for fast algorithm and hardware-sharing-based integer transform design are described. Finally, two case studies for fast algorithm and hardware-sharing-based architecture designs of discrete integer transforms are presented, where one is for the single-standard multiple-mode video transform-coding application, and the other is for the multiple-standard multiple-mode video transform-coding application.
Department of Electrical Engineering, National Chung Hsing University, Taichung, Taiwan, ROC
*Address all correspondence to: cpfan@dragon.nchu.edu.tw
1. Introduction
Video-coding system has generally utilized block-based transform-coding skills to shrink the data rates by joining quantization and entropy coding. Among some block-based transforms, the discrete cosine transform (DCT) [1] and integer transforms have extensively been used to still image and video-coding specifications, such as JPEG [2], MPEG-1/2 [3, 4], MPEG-4 [5], H.264/AVC [6, 7], AVS [8, 9], VC-1 [10], VP8 [11], and HEVC [12]. Because integer transforms perform the low complexity and effective coding performance, the advanced video coding (AVC) in ITU-T H.264 [6, 7, 13, 14], which is also known as MPEG-4 part 10, applies integer transforms for transform process. The 4 × 4 and 8 × 8 transforms in [13, 14] were calculated exactly to prevent non-adaptation issues of inverse transforms for high-quality moving visual images. The VC-1 specification [10, 15, 16] employed 4 × 4 and 8 × 8 integer transforms, and it was developed by Microsoft Corporation and standardized by the Society of Motion Picture and Television Engineers (SMPTE). The 8 × 8 integer transform is utilized to obtain the high-coding performance in the Audio Video Coding Standard (AVS) for China [8, 9]. In [11], the VP8 video-coding standard was developed for Internet browser applications. The Joint Collaborative Team on Video Coding proposed the high-efficiency video coding (HEVC) specification [12]. By HEVC, the compression efficiency was greatly better than that achieved using the H.264/AVC high-profile-coding specification.
To support the single-standard H.264/AVC video coding, several transform architectures in [17–24] have been developed to approach the multiple transform modes in H.264. To support the single-standard H.265/HEVC video coding, several transform architectures in [25–32] have been developed to approach the multiple transform modes in HEVC. Besides, supporting multiple-standard functions in video coding has been an important issue in multimedia applications recently, such as H.264/AVC, MPEG-1/2/4, VC-1, AVS, and VP8 standards, and several transform architectures in [33–41] have also been developed to complete the multiple transform functions. Owing to the growth of multistandard video-coding applications, how to achieve low-computational complexities and implement by hardware-sharing-based cost-effective architectures simultaneously are interesting research topics for the VLSI design of video codecs.
2. Matrix decomposition preprocessing for fast algorithm and hardware-sharing-based designs
Based on the resemblance property, the 8 × 8 inverse integer transforms [41] in H.264/AVC, AVS, VC-1, VP8, MPEG-1/2/4, and HEVC specifications are revealed in Eq. (1), and Table 1 depicts the coefficient values in the transforms.
In Eq. (2), A0 is divided into two modules, U4 × 4 and D4 × 4, where P1=[1000000−1010000−1000100−1000001−100000011000001001000100001010000001], Pr=[1000000000100000000010000000001001000000000100000000010000000001], A0=[afag0000ag−a−f0000a−g−af0000a−fa−g00000000−ed−cb0000−db−e−c0000−cebd0000−b−c−d−e].
Thus
A0=U4×4⊕D4×4E3
and C8×8 becomes
C8×8=P1⋅(U4×4⊕D4×4)⋅Pr.E4
In (3), “⊕ “ is the direct sum operator, and the two diagonal blocks U4 × 4 and D4 × 4 are processing in parallel. To cut down the computational operations and achieve effective hardware shares, the upper diagonal matrix U4 × 4 and the down diagonal matrix D4 × 4 are further decomposed into the cascaded multiplication form or the addition form of sparse matrices. After matrix factorizations, the chosen sparse matrices have the coefficients which are 1, −1, 0, or an integer, and an integer value can equal the combination of powers of two. Besides, zero factors in the chosen sparse matrices could be factorized as many as possible [42].
By Eq. (1), for VC-1 the values of the coefficient set {a, b, c, d, e, f, g} are {12, 16, 15, 9, 4, 16, 6}, and those for AVS are {8, 10, 9, 6, 2, 10, 4}. Next, those for MPEG-1/2/4 are {362, 502, 426, 284, 100, 473, 196}, and those for H.264/AVC are {8, 12, 10, 6, 3, 8, 4}. Finally, those for HEVC are {64, 89, 75, 50, 18, 83, 36}.
The general 4 × 4 inverse integer transform matrices [41] can be presented in Eq. (5) as
M4×4=[hihjhj−h−ih−j−hih−ih−j].E5
By Eq. (5), for VC-1 the values of the coefficient set {h, i, j} are {17, 22, 10}, and those for VP8 are {128, 167, 70}. Next, those for AVS-M are {2, 3, 1}, and those for H.264/AVC are {1, 1, 0.5}. Finally, those for HEVC are {64, 83, 36}.
3. Case study [32]: single-standard multiple-mode transform design
3.1. Hardware-sharing based 32 × 32 integer core transform for HEVC
The one-dimensional (1D) 32 × 32 inverse core transform for HEVC is described in [30]. By the symmetrical property, the 32 × 32 inverse core transform is presented as
Hi32=PA⋅CA1,E6
where CA1=[C11C12C21C22], PA=[I16x16−I˜16x16I˜16x16I16x16], I˜16x16=[00⋯0100010⋮⋮⋰0⋮010⋮010⋯00], and I16×16 is a 16 × 16 identity matrix. In Eq. (6), PA is the butterfly-like postprocessing, and CA1 is the sparse matrix. By swapping each column of CA1, it becomes
where PAr is the permutation matrix. In Eq. (7), CA2 is expressed by
CA2=[TA11016x16016x16TA22]=TA11⊕TA22,E9
where “⊕” means the direct sum operation, and then TA11 and TA22 are 16 × 16 matrices, which are revealed in [32]. The matrix PAr in Eq. (8) is expressed as
PAr=P(2,16),E10
where the permutation matrix P(m, n) is defined in [43], and the notation “⊗” means the Kronecker product. In Eq. (9), AA22 is presented as
TA22=TM1+TN1,E11
First, the lower half of CN1 is divided into sixteen 8 × 1 column vectors Xi, where i = 0, 1, 2, …, 15, and then TN1 becomes
TN1=[08x 16−−−−−−−−−X0X1…X15].E12
Second, the coefficients in a single column vector can be shared. The vector coefficient computations are achieved by integrating several base coefficients [32]. After realizing the column vectors of TN1, the lower half of TN1 is factorized as an integration of eight 1 × 16 row vectors depicted as Yi, where i = 8, 9, …, and 15, and TN1 becomes
TN1=[08x16−−−Y8Y9⋮Y15].E13
Adder tree structures are utilized to calculate the aggregate results for the row vectors Y8–Y15 [32]. By the duplicate operations for TN1, TM1 is presented as
TM1=[X^0⋯X^15−−−−−08x16],E14
where X^i is an 8 × 1 column vector, where i = 0, 1, 2, …, and 15. Then, TM1 becomes
TM1=[Y0⋮Y7−−−08x16],,E15
where Yi is a 16 × 1 row vector, where i = 0, 1, …, and 7. The realization of TM1 equals that of TN1. Finally, the operations of TM1 and TN1 are merged to TA22. The computational operations TA22 require 630 additions and 326 shift operations [32]. The matrix TA11 in Eq. (9), which is also denoted as Hi16, is the 1D 16 × 16 inverse core transform in HEVC [30].
3.2. Hardware-sharing-based 16 × 16 integer core transform for HEVC
The 16 × 16 integer core transform in [30] changes into
Hi16=PB⋅CB1,E16
where PB=[I8x8−I˜8x8I˜8x8I8x8], and CB1 is revealed in [32]. By swapping each column of CB1, it will be
CB1=CB2⋅PBr,E17
where PBr = P(8,2). By Eqs. (16) and (17), Hi16 is expressed by
where TM2=[−925−4357−7080−8790−2570−9080−43−957−87−4390−57−2587−70−980−578025−90987−43−7000000000000000000000000000000000], TN2=[00000000000000000000000000000000−704387−9−90−258057−80−9708725−57−90−43−87−57−94380907025−90−87−80−70−57−43−25−9].
By the duplicate processed of TN1 in Section 3.1, TN2 turns into
TN2=[04x8−−−−−−U0…U7],E21
where Ui is an 8 × 1 column vector, where i = 0, 1, 2, …, and 7. Next, TN2 also is
TN2=[04x8−−−V4⋮V7],E22
where Vi is a 1 × 8 row vector, where i = 4, 5, 6, and 7. Adder tree schemes are applied to compute the summed outcomes of V4–V7 [32]. By the same processes of TM1 in Section 3.1, TM2 becomes
TM2=[U^0…U^7−−−−−−04x8],E23
where U^i is a 4 × 1 column vector, where i = 0, 1, 2, …, and 7. Next, TM2 also is
TM2=[V0⋮V3−−−04x8],E24
where Vi is a 1 × 8 row vector, where i = 0, 1, 2, and 3. Then, adder trees are used to treat the row vectors V0–V3 [32]. Finally, the calculations of TM2 and TN2 are merged to TB22. The computational operations of TB22 are 164 additions and 106 shift operations [32]. Meantime, the TB11 in Eq. (19), which is also denoted as Hi8, is the 1D 8 × 8 inverse core transform in HEVC [30].
3.3. Hardware-sharing-based 8 × 8 integer core transform for HEVC
The 8 × 8 integer transform in [30] is described as
Hi8=PC⋅CC1,E25
where PC=[I4x4−I˜4x4I˜4x4I4x4], and CC1=[640830640360640360−640−830640−360−640830640−830640−3600−180500−750890−500890−180−750−750180890500−890−750−500−18]. After swapping each column in CC1, it changes into
CC8=CC2⋅PCr,E26
where PCr=[1000000000100000000010000000001001000000000100000000010000000001]. Based on Eqs. (25) and (26), Hi8 is presented by
where S1=[−180089089−180018890−8900−18]. Moreover, S1 is expressed by
S1=Z1+(18⋅Z2),E30
where Z1=[000−10−10000−101000] and Z2=[−100505−100150−500−1]. In Eq. (29), S2 is presented as
S2=25⋅Z3,E31
where Z3=[02−30−200−3−30020−3−20]. By Eqs. (29)– (31), TC22 becomes
TC22=Z1+(18⋅Z2)+(25⋅Z3).E32
In Eq. (32), the computations of TC22 require 36 additions and 28 shift operations [32]. The matrix TC11 in Eq. (28) is also the 1D 4 × 4 inverse core transform matrix in HEVC.
3.4. Hardware-sharing-based 4 × 4 integer core transform for HEVC
The 4 × 4 integer core transform matrix is indicated as
Hi4=PD⋅CD1,E33
where PD=[10100101010−110−10] and CD1=[640640640−6400−360830−830−36]. By swapping each column of CD1, it changes into
CD1=CD2⋅PD2.E34
where PDr=[1000001001000001]. From Eqs. (33) and (34), Hi4 is described by
where Z4=[111−1]. In Eq. (36), TD22 is indicated by Z5 and Z6 as
TD22=36⋅Z5+11⋅Z6,E38
where Z5=[211−2] and Z6=[100−1]. Thus, the computations of TD22 are 10 additions and 10 shift operations [32]. Based on Eqs. (35)– (38), Hi4 is changed into
Hi4=PD⋅[(64⋅Z4)⊕(36⋅Z5+11⋅Z6)]⋅PDr.E39
By the abovementioned discussions, the hardware modules of 4 × 4, 8 × 8, and 16 × 16 inverse core transforms are shared to implement Hi8, Hi16, and Hi32, respectively [32]. By sharing the hardware of Hi4 in Eq. (39), the cost-effective design of the 8 × 8, 16 × 16, and 32 × 32 inverse core transforms is obtained progressively. First, the hardware-sharing-based eight-point inverse transform is presented as
Hi8=PC⋅{Hi4⊕[Z1+(18⋅Z2)+(25⋅Z3)]}⋅PCr.E40
Next, the hardware-sharing-based 16-point inverse transform is described as
Hi16=PB⋅{Hi8⊕[TM2+TN2]}⋅PBr.E41
Finally, the hardware-sharing-based 32-point inverse transform is depicted as
Hi32=PA⋅{Hi16⊕[TM1+TN1]}⋅PAr.E42
In this section, the hardware-sharing transform architecture cuts down the hardware cost because the same submodules and coefficients of the transforms are extracted to be shared. Figure 1 illustrates the architecture of the hardware-sharing-based inverse core transform design for 4 × 4/8 × 8/16 × 16/32 × 32 transforms [32].
3.5. Architecture comparison
The proposed 1D inverse core transform in [32] involves four inputs to sustain 4 × 4, 8 × 8, 16 × 16, and 32 × 32 transform modes. Several multiplexers are utilized to acquire the transform outputs of the 32 × 32 inverse core transform by the shared design of 4 × 4, 8 × 8, and 16 × 16 inverse core transforms [32]. Table 2 lists the number of adders and shifters needed to calculate four modes of the 1D inverse core transform for HEVC. The developed architecture in [32] does not require any multiplier, and the fixed-coefficient multiplications are replaced with simple additions and shift operations. Table 3 shows the comparison of three 16-point inverse transform designs. Compared with the previous works in [29] and [31], the applied architecture contains fewer adders. However, several more shifters are required. Compared with the cost of adders, the shifters need lower hardware expense. Thus, the used architecture decreases the hardware cost more efficiently than previous transform schemes do.
Figure 1.
The hardware-sharing-based inverse core transform structure for HEVC.
Transform sizes
32 × 32
16 × 16
8 × 8
4 × 4
No. of shifters
256
93
40
11
No. of adders
461
146
64
10
Table 2.
The 1D inverse transform architecture at different transform modes [32].
4. Case study [41]: multiple-standard multiple-mode transform design
4.1. Hardware-sharing design for 8 × 8 transforms mode
For H.264/AVC, the transform matrix is employed as a foundation matrix for the multistandard hardware-sharing scheme. Based on Eq. (3), the cost of the upper diagonal matrix in Eq. (43) is eight adders and two shifters.
U4×4_AVC=[888484−8−88−4−888−88−4]=8⋅C1⋅C2,E43
where C1=[10010−1100110100−1], and C2=[10100−0.50110−100100.5]. For AVS, the upper diagonal matrix U4×4_AVS in Eq. (44) costs 10 adders and four shifters.
where and C4=[00000000.5000000.500], and C5=[1.500001.500001.500001.5]. For HEVC, the 8 × 8 transform matrix is acquired by the AVS design in Eq. (44), and the design in Eq. (46) costs 16 adders and 12 shifters.
where U2=[2202200000220−2200000],and U3=[00000403900000390−4]. In Eq. (47), the parameter “22” of U2 is implemented by (C5 · C5 ≪ 4) – (C1 ≪ 1), where “≪1” is left shifting one bit, and the cost in Eq. (47) requires 28 adders and 26 shifters.
By Eq. (3), on the other side, the down diagonal matrix D4×4_AVC for H.264/AVC becomes Eq. (48), and it needs 17 adders and eight shifters.
where U4=[100001000010000−1], D4=[−1−110101−1−110−10111], D5=[−0.5000000.5000.5000000.5], D2=[0.2500000.250000−0.2500000.25], U3=[000−1001001001000].
For AVS, the D4×4_AVS matrix becomes (49), and D4 and D5 are shared with the design in Eq. (48), and then U3 and U4 are also partially shared with the scheme in Eq. (48). In Eq. (49), it costs 24 adders and 12 shifters
where U5=[00−10000110000100], U6=[0−1001000000−10010], U7=[000101000010−1000]. For MPEG-1/2/4, based on D4×4_AVS, the D4×4_MPEG matrix is presented by Eq. (52), and the design costs 48 adders and 32 shifters
where U9=[10100−20610−100602]. For VP8, all coefficients in 4 × 4 transform matrix are multiplied by 128 to get integer values, and it costs 18 adders and 14 shifters
where U10=[00000−6039000003906]. The matrix U4×4_AVC/8 equals the 4 × 4 inverse transform matrix in H.264/AVC. In addition, the matrix U4×4_HEVC equals the 4 × 4 inverse transform matrix in HEVC. Thus, several multiplexers are used to share the hardware between the submatrices to decrease hardware cost.
4.3. Architecture comparison
The applied hardware-sharing-based 1D multistandard inverse integer transform scheme has two inputs, which sustain 4 × 4 and 8 × 8 transform modes. The hardware blocks of processing the 4 × 4 inverse transforms are shared with that of the upper diagonal matrix U8×8. Thus, several multiplexers are utilized for U8×8 to compute the 4 × 4 inverse transforms without additional operations. For the multistandard applications, the hardware-sharing architecture of the fast 1D 4 × 4 and 8 × 8 inverse integer transforms is illustrated in [41]. The shifters are also realized by wiring. Compared with the individual designs without hardware shares, Table 4 depicts that the used scheme in [41] decreases the number of shifters and adders by 50 and 75%, respectively.
Different 1D inverse integer transform modes
No. of adders
No. of shifters
Individual designs without hardware shares
336
180
Hardware-sharing-based design in Section 4
82
90
Reduction of cost
75%
50%
Table 4.
Hardware comparison between two architectures [41].
To implement the discussed architecture, a cell-based VLSI design flow is utilized to design, simulate, and verify the cost-effective hardware-sharing architecture. For fair comparisons among different transform structures, the normalized mode gain, which is required to normalize the gate counts, is described as follows: By matrix dimensions and without missing generality [40], the normalized mode gains defined for the 32 × 32, 16 × 16, 8 × 8, and 4 × 4 inverse integer transform matrices are 16, 4, 1, and 1/4, respectively.
The hardware-sharing-based design in Section 3 supports 4 × 4, 8 × 8, 16 × 16, and 32 × 32 inverse transform modes for HEVC. Thus, the normalized mode gain of the design is 21.25 (i.e., 16 + 4 + 1 + 0.25). Similarly, five 8 × 8 and five 4 × 4 inverse transform functions are provided by the hardware-shared design in Section 4. Therefore, the normalized mode gain is assigned by 6.25 (i.e., 5 + 1.25) [41]. Afterwards, the normalized gate counts are defined by [40, 41]
Table 5 shows the hardware cost comparisons among different 1D multiple transform architectures, which includes single-standard multiple-mode [32] and multiple-standard multiple-mode [41] transform designs.
For the single-standard multiple-mode transform design, this chapter discussed the 4 × 4, 8 × 8, 16 × 16, and 32 × 32 inverse core transforms in HEVC with a cost-effective and hardware-efficient design. By the symmetrical characteristics of the elements, the core transform matrices were factorized into several submatrices. Thus, the hardware of the (N/2) × (N/2) inverse core transform was shared with that of the N × N inverse core transform for N = 32, 16, and 8. Compared with the direct design without hardware shares, the applied transform scheme in Section 3 decreased the hardware cost of adders and shifters by 32 and 36%, respectively. Besides, for VLSI implementation, the design in Section 3 requires less normalized gate counts than the design does in [29].
For the multiple-standard multiple-mode transform design, this chapter also discussed the fast algorithm and hardware-sharing-based design of 4 × 4 and/or 8 × 8 inverse transforms among H.264/AVC, VC-1, HEVC, MPEG-1/2/4, AVS, and VP8 for multistandard video decoders. By only shifters and adders, the decomposition scheme of matrices was used to develop the hardware-shared scheme. The used structure in Section 4 decreased the number of shifters and adders by 50 and 75% more than the individual fast algorithm-based implementation did. Besides, for VLSI implementation, the design in Section 4 requires less normalized gate counts than the designs do in [26, 28, 36, 38].
This work was supported by Ministry of Science and Technology, Taiwan, R.O.C. under Grant MOST 105-2221-E-005-078.
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Written By
Chih-Peng Fan
Submitted: 09 March 2016Reviewed: 21 July 2016Published: 23 November 2016
Open access peer-reviewed chapter
