Optimised design parameters of Si/SiC DD hetero-structure IMPATTs for large-signal analysis.

## 1. Introduction

Among the microwave and MM-wave solid-state devices, IMPact Avalanche Transit Time (IMPATT) device has emerged as the most efficient and powerful source of MM-wave power. Most of the current research activities for MM-wave systems are focused on the design and development of IMPATT devices at MM-wave window frequencies, i.e., 35, 94, 140, 220 GHz, where atmospheric attenuation is relatively low. These devices are finding important applications in tracking radars, missile guidance, battle field communication, collision avoidance system and radiometers. IMPATT diodes based on Si, GaAs, InP have been experimentally realized to provide sufficient power at MM-wave frequencies. For realizing higher RF power (P_{RF}) from an IMPATT device, one should choose a semiconductor material that has higher value of critical electric field (E_{c}), saturated drift velocity (v_{s}) & thermal conductivity (K), since P_{RF} from an IMPATT device is proportional to E_{c} ^{2}.v_{s} ^{2}. The excellent material properties of WBG semiconductors suggest that WBG semiconductor based IMPATT devices are the future MM-wave sources. With the advent of new technologies for growth of SiC crystals, researchers are showing renewed interest in exploring the possibilities of extracting more power from SiC-based IMPATT devices. The experimental research on the development of SiC-IMPATTS is underway. On the other hand, IMPATT device technology based on Si is well established over a wide frequency range. The authors have therefore chosen Si/SiCbased hetero-structure IMPATT diodes, to simulate the large signal properties of the device at W-band (75-110GHz). The authors have developed a generalized technique based on self-consistentmodel for large-signal simulation of SiC DDR IMPATT devices.

Several methods for the large-signal analysis of IMPATTs and other negative resistance devices are reported in the literature [1-5]. Earlier reported large-signal modelling are basically analytical modelling of *Read-diodes* with some simplifications and restrictive assumptions, such as, equal carrier velocities, ionization rates of electrons and holes, punched through depletion layer boundaries, non-inclusion of mobile space charge effects. Consequently in their analysis, the generated power increases monotonically with the increasing RF amplitudes i.e. those analyses do not exhibit saturation effects and this constitutes an important limitation in applying those type of models. The authors have assumed a sinusoidal current at the input of the Si/SiC double drift device and obtained the corresponding voltage response to calculate the device impedance. In the present paper the author has formulated a simple and generalized method for large-signal simulation of Si/SiC IMPATTs at 94 GHz based on current excitation at the input of the device. The large-signal impedance as a function of frequency has been obtained by considering the fundamental frequency and higher harmonic terms.

## 2. Modelling and Simulation Technique

Numerous computer based models, those are appeared in the earlier literatures, may be divided into two main categories:

Analytical modeling of Read diodes with some simplifications and restrictive assumptions, such as, equal carrier velocities, ionization rates of electrons and holes, punched through depletion layer boundaries, non inclusion of mobile space charge effects. Consequently in their analysis, the generated power increases monotonically with the increasing RF amplitudes i.e. those analyses do not exhibit saturation effects and this constitutes an important limitation in applying this type of model.

The second type of large signal model is defined as ‘full-scale-simulation’ with again some assumption.

Though the full scale simulation is applicable to wide variety of structures and they can allow for realistic physical processes at large RF amplitudes, they are difficult to program and time consuming to run on a routine basis. In addition to this, numerical instability appears to be a common problem with these simulations, particularly at larger RF amplitudes.

The purpose of this article is to describe an alternative to the generally unrealistic and/or time consuming and complicated approach of earlier analytical and numerical methods. In essence, the present full-scale program employs a generalized, non-linear analysis of a p^{+} p n n^{+} type SiC based Double Drift IMPATT device, without any drastic assumption. In this self-consistent single frequency analysis of IMPATT diodes, the modified ‘field-maximum method’is used to obtain the detailed ‘snap-shot’ of the electric field, hole and electron current density as function of active region width during one complete cycle of steady-state oscillation. This program takes into account the non-linear model that contains the differential equations for the carrier concentrations, current density equations, un-equal values of field dependent carrier ionization rates, mobile space charge effects, the behavior of charge carriers and their interactions with electric filed as well as most of the physical effects, such as elevated temperature effects, parasitic effects etc., pertinent to IMPATT operation. With this program it is possible to obtain large signal admittance and impedance of the diode, RF power output as well as other important properties of the device at larger amplitudes of RF signal. A drift-diffusion model has been used for the large-signal analysis. A time varying electric field is assumed in the form, *ξ = ξ* _{p }*+ m* _{x }*ξ* _{p }*sin (ωt) + m* _{x }^{2 }*ξ* _{p }*sin (2ωt) +………*, where *ξ* _{p }is the DC peak electric field and *m* _{x }is the modulation factor. The value of *m* _{x }can be varied to study the effect of field modulation on the large signal properties of IMPATT device. The physical phenomena take place in the semiconductor bulk along the symmetry axis of the mesa structure of IMPATT diodes.

The fundamental device equations i.e., Poison’s equation (equation (1)), continuity equations (equations (2)& (3)) and current density equations (equations (4)& (5)) involving mobile space charge in the depletion layer are simultaneously solved under large-signal condition by using appropriate boundary conditions by using a double iterative field maximum computer method described below. The fundamental device equations are given below.

Where the symbols *α* _{n }, *α* _{p }, *v* _{n }, *v* _{p }, *μ* _{n }, *μ* _{p }, etc. have their usual significance.

In the above mentioned simulation method, the computation starts from the field maximum near the metallurgical junction. The boundary conditions for the electric field at the depletion layer edges are given by,

Similarly the boundary conditions for normalized current density *P(x,t) = (J* _{p }*(x,t) – J* _{n }*(x,t)) / J* _{0 }*(t)* (where, *J* _{0 }*(t) = J* _{p }*(x,t) + J* _{n }*(x,t)*) at the depletion layer edges ie, at *x = -x* _{1 }and *x = x* _{2 }are given by,

*M* _{n }*(x* _{2 }*,t)* and *M* _{p }*(-x* _{1 }*,t)* are the electron and hole multiplication factors at the depletion layer edges are given by.

The initial values of electron and hole densities are either furnished by a previous run or are given by the quiescent zero bias solution, i.e. solution when

The breakdown voltage at any time instant is calculated by integrating the spatial field profile over the total depletion layer width, i.e.

The magnitude of peak field at the junction (*ξ* _{p }), the widths of avalanche and drift zones (*x* _{A }and *x* _{D }; where *x* _{D }*= d* _{n }*+ d* _{p }), breakdown voltage (*V* _{B }) and the voltage drops across these zones (*V* _{A }, *V* _{D }= *V* _{B }*- V* _{A }) are obtained from double iterative DC simulation program at *t = 0*. The snap-shots of electric field and current density profiles in the depletion layer of IMPATT diodes can be obtained from the simultaneous numerical solution of the basic device equations (equations (1) – (5)) subject to appropriate boundary conditions (equations (6)& (7)). A software package has been developed for simultaneous numerical solution of the above said equations. Boundary conditions are imposed at the contacts (at the *n* ^{+ }*-n*& *p* ^{+ }*-p* contacts) by setting up the appropriate restrictions in equations (1) – (5).

The evaluation of current and voltage in time & space domain of the device and the equivalent circuit has been obtained through the developed simulation program. The total terminal current (i.e. the external current) is given by,

Where, *C* _{d }is the depletion region capacitance of the diode, *V(t)* is the AC terminal voltage and *I* _{e }*(t)* is the terminal current induced by the transport of carriers through the diode (Fig. 2). The optimized design parameters are obtained after several computer runs. Once the snap-shots of electric field and current profiles at different time & space over a complete cycle are obtained, the optimized values have been used for simulation of large-signal impedance and admittance characteristics of the device. The diode admittance (including the depletion region capacitance (*C* _{d }) at the oscillation frequency *ω* is given by the fundamental frequency components of current and voltage by,

Finally the expression governing the terminal voltage *V(t)* is given as [7],

Where,

Simultaneously,

The fundamental frequency component of *V(t)* is found by a Fourier analysis of (13) and is given as,

After *I* _{e }*(t)* and *V* _{1 }*(t)* in equations (15) and (17) are represented as phasors and substituted into equation (12), the diode admittance is found to be,

A generalized large-signal program has been developed to solve the equations (12), (13), (17) and (18). The symbols have their usual significance. The simulation is carried out by considering a space division of *500* steps and time scale is varied from *100-150* to increase the accuracy of the simulation. Material parameters of SiC is taken from NSM archive [6].

## 3. Results and Discussions

The optimized structural parameters of Si/SiC DD hetero-structure IMPATTs for operation at W-band are given in Table 1 for the bias current density of 8x10^{8} A/m^{2}. Figures 3(a-c) denotes the voltage and current waveform for SiC IMPATT device operating under large-signal condition. The plots depict the 180^{0} phase-shift between voltage and terminal current, essential criteria for IMPATT oscillation. This proves the validity of the simulation software. Large-signal simulation provides the snap-shots of electric-field profiles at different phase angles as shown in figures 4(a) to 4(e). The electric field increases from t=0 and attains its peak value in the positive half-cycle at t =T/4 (E_{max} = 5x10^{8} V/m) as shown in figure 4(b). It then decreases and attains the same magnitude of negative peak in the negative half-cycle at t = 3T/4., as shown in figure 4(d). The program is also run for the second and consecutive cycles and it is observed that the above nature of variation of electric field is repeated in each and every cycle.

The effect of voltage modulation on the large-signal negative resistance, reactance, RF power, efficiency, negative conductance and Q-factor of the device has been studied and the results are presented in this paper. Large-signal admittance plots (conductance versus susceptance) for different modulation factors are shown in figure 5. It is observed that the magnitude of peak negative conductance decreases from 37.5x10^{6} S/m^{2} at 94 GHz to 5.0 x10^{6} S/m^{2} when voltage modulation increases from 10% to 50%, i.e., corresponding RF voltage increases from 20.0V to 104.0 V. In the limiting case of RF-voltage being very low, the large-signal peak negative conductance value should approach the small-signal value. When RF voltage modulation is very low, i.e., 2% and the RF voltage amplitude is 4.0V, the simulated large-signal negative conductance is 43.5x10^{6} S/m^{2}. The authors have also carried out small-signal simulation of the Si/SiCdevice based on Gummel-Blue approach and obtained the admittance plot with the same design structural parameters to verify whether the peak negative conductance under small-signal condition approaches that under large-signal condition with negligibly small voltage modulation of 2%. It is observed from Figure 5 that the large-signal admittance plot for lowest voltage modulation almost coincides with the simulated small-signal admittance plot which verifies the validity of the proposed large-signal modeling of the device.

Structure | Diode conductance (-G x10 ^{6})(Sm ^{-2}) | Diode Susceptance (B x 10 ^{6})(Sm ^{-2}) | -ZR (for 2% modulation (Ω) | R_{S}(Ω) | Expected load conductance (G _{L} x 10^{6})(Sm ^{-2}) | Rs, total (including p ^{+}& n^{+}ohmic contact) |

Si/SiCDD hetero-structure | 35.0 | 80.0 | 6.0 | 0.5 | 32.0 | 2.3 |

Fig. 6 shows the variation of RF output power with RF voltage. It is interesting to observe that under large-signal condition RF power initially increases with the increasing voltage modulation, reaches a peak value at 50% voltage modulation and then decreases with further increase of voltage modulation. Figure 6 shows the variation of efficiency with RF voltage. It is observed that the efficiency increases with increase in RF voltage, attains a peak value corresponding to 50% voltage modulation and then starts decreasing. It is observed that, with the increasing amplitude of RF voltage from 21.0V to 104.0 V, the magnitude of negative resistance of the device decreases from 10.0 Ω to 6.0 Ω. The analysis shows the variation of negative reactance of the device for different voltage modulation. It is observed that the magnitude of negative reactance increases from 13.0 ohm to 14.5 ohm when RF voltage increases from 10% to 50%. The variation of negative reactance with RF voltage is sharper than that of the negative resistance with RF voltage. At 94 GHz window, the increase in Q-factor from 1.0 to 6.0 with change in RF voltage from 21.0V to 104V, as expected. Large-signal Q-factor for a particular RF voltage indicates the overall RF performance of the device.

Diode | n and p epilayers doping conc. (N _{D,A})(10 ^{23} m^{-3}) | Width of n and p epilayers (W _{n,p})(µ) | Depletion layer capacitance (pF) | DC breakdown voltage (V) | Transit Time (pS) | Junction area (10 ^{-9}m^{2}) | Si (substrate) layer width (µ) |

Si/SiC DD hetero-structure | 2.2 | 1.105 | 0.11 | 207.6 | 5.525 | 1.0 | 4.0 |

## 4. Conclusion

The author has developed a generalized technique for large- signal simulation of DDR SiC IMPATT diode. This simulator is applicable for other WBG semiconductor based IMPATTs and also for different structures and doping profiles of the device. The validity of the proposed technique is verified from the simulated small-signal admittance plot. The results show for DC breakdown voltage of 207.0 V the large-signal (for ~ 50% voltage modulation) power output and efficiency are 25.0 W and 15.0%, respectively. To the best of author‘s knowledge, this is the first report on non-linear analysis of 4H-SiC IMPATTs at W-band.

## Acknowledgments

Moumita Mukherjee wishes to acknowledge Defence Research and Development Organization (DRDO), Ministry of Defence, Govt. of India, and University Grants Commission (UGC), Govt. of India, for providing her financial assistance to carry out this study. The author is thankful to Director CMSDS, Dr. P. Datta, for his keen interest in this work. The author also gratefully acknowledges Prof. S. K. Roy, founder Director - CMSDS and Professor, IRPE, University of Calcutta, Prof. N. Mazumder, West Bengal University of Technology, India, Prof. J. P. Banerjee, former Director, CMSDS and Prof. D.N.Bose, Emeritus Professor, Calcutta University, for their valuable suggestions and important comments during the development of the simulator.