Open access peer-reviewed chapter

Ladder Diagram Petri Nets: Discrete Event Systems

By José Carlos Quezada Quezada, Ernesto Flores García, Joselito Medina Marín, Jorge Bautista López and Víctor Quezada Aguilar

Submitted: November 17th 2017Reviewed: February 21st 2018Published: September 19th 2018

DOI: 10.5772/intechopen.75753

Downloaded: 258

Abstract

Ladder diagram language (LD) is a common programming language in industry to develop control algorithms of discrete event systems (DESs). Besides, it is one of the five programming languages supported by the International Electrotechnical Commission through the IEC-61131-3 standard. On the other hand, Petri net (PN) theory is both a graphical and mathematical tool used to model discrete event systems, particularly in this study, control lines used in industrial algorithms. Control algorithms in LD are generally developed based on the experience of control system programmers. Therefore, it is still a relevant problem how to formalize the current and new control algorithms. In this chapter, are analyzed lines in LD used more frequently in control algorithms. Additionally, an element-to-element transformation methodology from a LD program to a PN model is proposed.

Keywords

  • control algorithms
  • discrete event systems
  • ladder diagram language
  • model
  • petri nets

1. Introduction

LD language is one of the five languages contemplated in the standard IEC-61131-3 [1], its use in the industry is due to its similarity with the electrical diagrams, and its behavior is based mainly on the electromechanical relay, but LD language also has the capacity to include logical functions blocks. The others languages are: function block diagram (FBD), instructions list (IL), structured text (ST) and sequential function char (SFC).

There are two types of control lines that are analyzed and converted into PN structures: the logical AND, OR, AND-OR, auto-loop and interlocking, which have both discrete inputs and outputs. The logic blocks such as timer, counter and comparator have all analog inputs, but their control output is discrete.

The main motive or need to model the control algorithms in LD is because they are developed mainly based on the experience of programmers in industrial control [2, 3], so it is important to propose approaches that help guarantee the safe control algorithms applied in machines or industrial processes, and the theory of PN [4] allows modeling the basic control lines used in the LD algorithms. Different approaches have been presented to provide a solution to analyze, model and simulate control algorithms developed in LD with PN or vice versa [5, 6, 7, 8, 9, 10, 11].

Physical or discrete memory signals can have two states (activated or deactivated, 0 or 1, etc.), so, we propose a distribution of these signals to PN structure that can model both states, but only one active at a time. On the other hand, the cyclic operation of PLC generates cyclic evaluation of the control algorithm in function of the states of physical input and memory signals. This behavior must be considered to avoid accumulation of tokens in places of PN structures, for which reason marking conditions are proposed in places that represent physical or memory outputs of PN structures of control lines in LD. Likewise, cyclic evaluation of control lines generates the energized and de-energized behavior of coils; therefore, it is also necessary to restore conditions of PN structures of each control line in LD, conditioning the marking in function of the input places [12, 13].

To convert control lines with analog inputs, places where their marking is a data (color in colored Petri nets) are included [9], which may be changing depending on the logic control algorithm. Conditioned transitions are proposed for their firing depending on the behavior of the control block in respective LD.

Based on analysis of the control lines, we propose the definition of a PN for discrete event systems in LD (LDPN), with which PN structures of control lines in LD are generated.

2. Control lines in LD to discrete event systems

The LD language has as its operating principle the behavior of an electromechanical relay, with the option of including function blocks. The standards IEC-61131-3 define LD like “modeling networks of simultaneous functioning electromechanical elements, such as relay contacts and coils, timers, counters, etc.” The control lines analyzed are the logic AND, OR, AND–OR, auto-loop, interlocking, timers, counters and mathematic comparisons. The first five logical have discrete inputs and output. Meanwhile in the logical of timers, counters and mathematical comparisons have analog inputs and discrete outputs.

The run of control algorithm in PLC is cyclic, and it mainly performs five actions such as reading of physical inputs, copy status of physical inputs, evaluation of the control algorithm with previous copy, copy of the status of physical outputs and sending of these statuses to physical modules.

2.1. Control lines both discrete inputs and outputs

Figure 1 shows the control line of logic AND, when all contacts In_1, In_2, …, In_n allow electric power flow, then Out1 coil is energized. Eq. (1) is the model corresponding.

Out1=In_1&&In_2&&In_nE1

Figure 1.

Control line of logic AND.

Figure 2 shows the control line of logic OR, when any contact In_1, In_2, …, In_n allows electric power flow, then Out1 coil is energized, its model is stand for the Eq. (2).

Out1=In_1In_2In_nE2

Figure 2.

Control line of logic OR.

Figure 3 shows the control line of logic AND–OR. When the contacts In_1, In_2, …, In_n or the contacts In_1, In_3, …, In_n allow electric power flow, then Out1 coil is energized. Eq. (3) is the model corresponding.

Out1=In_1&&In_2&&In_nIn_1&&In_3&&In_nE3

Figure 3.

Control line of logic AND–OR.

Figure 4 shows the control line of logic auto-loop. When the contacts In_1, In_2, …, In_n or the contacts Out1, In_2, …, In_n allow electric power flow, then Out1 coil is energized. Eq. (4) is the model corresponding.

Out1=In_1&&In_2&&In_nOut1&&In_2&&In_nE4

Figure 4.

Control line of logic auto-loop.

Figure 5 shows the control line of logic interlocking, when the contacts In_1, ~Out2, …, In_n allow electric power flow, then Out1 coil is energized, and it blocks the energizing of Out2 coil. If Out2 coil is energized first, then Out1 coil cannot be energized. Eq. (5) is the model corresponding.

Out1=In_1&&Out2¯&&In_n;Out2=In_2&&Out1¯&&In_mE5

Figure 5.

Control line of logic interlocking.

2.2. Control lines with analog inputs and discrete output

Figure 6 shows the standard function block of on-delay timer (TON) and its timing diagram of the functional [1]. The signals Preset_time and Elapsed_time are analog. If the contact In_1 allows electric energy flow, when Elapsed_time adds base time and if Elapsed_time is equal or greater than Preset_time, then Out1 coil is energized. Eq. (6) depicts the logic model of the block TON.

IfIn_1=1&&ETPT,then Out1=1E6

Figure 6.

On-delay timer.

Restart condition: If In_1=0,thenET=0and Out1 = 0.

Figure 7 shows the standard function block of off-delay timer (TOF) and its timing diagram of the functional [1]. If the contact In_1 allows energy power, then the Out1 coil is energized, and the Elapsed_time variable is set to zero. When the In_1 signal is equal to zero, the Elapsed_time variable adds base time and if Elapsed_time is equal or greater than Present_time, then Out1 coil is de-energized. Eq. (7) shows the logic model of block TOF.

IfIn_1=0&&ETPT,then Out1=0E7

Figure 7.

Off-delay timer.

Restart condition: If In_1=1,thenET=0and Out1 = 1.

Figure 8 shows two counter function blocks: (1) up-counter and (2) down-counter. In both blocks, the contact In_1 is the pulse to counter, that is and positive transition is detected; if the contact In_2 allows electric energy flow, then Out1 coil is de-energized, and the Current_value variable is set to zero in up-counter and to Preset_value in down-counter. In up-counter, if Current_value is equal or greater than Preset_value, then Out1 coil is energized. In down counter, if Current_value is equal to zero, then Out1 coil is energized. Eqs. (8) and (9) are logic models of the counters, respectively.

if In_1,thenCV=CV+1;ifIn_2=0&&CVPV,then Out1=1E8

Figure 8.

Counters. a) Counter up, b) Counter down.

Restart condition: If In_2=1,thenCV=0

if In_1,thenCV=CV1;ifIn_2=0&&CV0,then Out1=1E9

Restart condition: If In_2=1,thenCV=PV.

Figure 9 shows the standard comparison function blocks: a) equal to, b) lower than and c) greater than. In all the blocks, two analog signals are compared, and depending on result is energized or de-energized Out1 coil. The logic models, respectively, are specified in Eqs. (1012).

If Value_1=Value_2,then Out1=1E10
If Value_1<Value_2,then Out1=1E11
If Value_1>Value_2,then Out1=1E12

Figure 9.

Mathematical comparisons. a) Relation, equal to, b) Relation, lower than, c) Relation, greater than.

3. Model of control lines in PN

In this section, the bases of the PN theory are indicated, and the discrete-LDPN network, which is the basis for generating the PN structures of the control lines in LD, is defined. Likewise, the conditions for marking places and triggering transitions are described to model the cyclical evaluation behavior of the control algorithm in PLC.

3.1. Petri nets

PN are a graphic and mathematic tool mean to modeling DES behavior. Graphically, a PN uses circles in order to represent places, rectangles to represent transitions and arcs with arrow or circle to link the inputs and output places with a transition. The relation between places and transition can be represented mathematically by means of an incidence matrix. For a PN with n transitions and m places, its incidence matrix A=aijis an integer number matrix representing the weighting of the input and output arcs; aij+represents the weighting of output arcs from transitions and aijrepresents input arcs to transitions. Eq. (13) represents how the incidence matrix values are obtained.

aij=aij+aijE13

To model the dynamic behavior of DES, PN has the state equation, which shows the marking in the net sequentially from initial marking Mk1and when applying a firing vector ukto the transpose of the respective incidence matrix AT, respectively. Eq. (14) shows the relationship between them.

Mk=Mk1+ATukE14

3.2. LDPN: Discrete event systems

In an LD control algorithm, a discrete signal can have n contacts normally open and m contacts normally closed. The work in [12] shows a representation of discrete signals used in LD to PN, which is the base of conversion of control lines that have both discrete inputs and outputs. On the other hand, evaluation of control algorithm in PLC is cyclical, which generates two important conditions to consider in the PN model; the cyclical evaluation in PN would generate accumulation of marks in the places, and in function of the logic, marking and consuming of theses in places that represent coils in the LD. This last condition is also necessary to restore the information of places in PN that represent physical analog signals or memory registers. Figure 10 shows the distribution of discrete signals in PN, and Eq. (15) its interpretation. Only one transition can be enabled at a time; if the input place does not have a mark, then the transition IOBcis enabled for inhibitor arc. Eq. (16) is the generalization of the marking of I, O y B places.

Ii=InoImc;Oo=OnoOmc;Bb=BnoBmcE15

where the subscripts n and m are not necessarily equal.

MIOB=01,thenMIOBo=0andMIOBc=1MIOBo=1andMIOBc=0E16

Figure 10.

Distribution of discrete signals in PN.

Considering symbols of [3], for a pre-set and post-set of places, are defined:

t=p:ptF, the set of input places of t.

t=p:tpF, the set of output places of t.

For tokens accumulation problem in input places, the Eqs. (17) and (18) are proposed. Both equations are is in function of the marking of inputs places and of output place. Eq. (17) is for structures with logic AND, and Eq. (18) for logic OR.

OBt=Mt=1&&OBt=0E17
OBt=Mt=1&&OBt=0E18

In the same way, to consume token in output place and restoring conditions of PN structures, Eqs. (19) and (20) are defined, which are in function of both marking input places and output places.

RCt=Mt=0&&OBt=1E19
RCt=Mt=0&&OBt=1E20

From the above, the ladder diagram Petri net: discrete event systems is defined as it is shown in Table 1 .

A Discrete-LDPN is a 5-tuple (P, T, W, F, M 0 ), where:
P=IOBAIARRCis a finite set of places, where:
I=I1I2Iiis a finite set of places that represent discrete physical inputs,
O=O1O2Oois a finite set of places that represent discrete physical outputs,
B=B1B2Bbis a finite set of places that represent discrete memory signals,
AI=AI1AI2AIaiis a finite set of places that represent analog physical inputs,
AR=AR1ARI2ARaris a finite set of places that represent analog memory signals,
RC=RC1RC2RCrcis a finite set of places to restart condition of the nets and its marking it in function of the states of inputs and outputs of control line type.
T=IcoOcoBcoLAIRCis a finite set of transitions, where:
Ico=I1coI2coIicois a finite set of transitions that have discrete physical inputs,
Oco=O1coO2coOocois a finite set of transitions that have discrete physical outputs,
Bco=B1coB2coBbcois a finite set of transitions that have discrete memory signals,
L=L1L2Llis a finite set of transitions that may have places of discrete signals,
AI=AI1AI2AIaiis a finite set of transitions that can have discrete and/or analog signals, its fire condition it in function of mathematics or logics restrictions.
RC=RC1RC2RCrcis a finite set of transitions that have input place RC to restart condition of PN structure.
FP×TT×Pis a set of arcs.
W=F1, all weights of the arcs are equal to 1.
M0=P01,discrete signal.PZ16bitinteger,analog signal.

Table 1.

Definition of LDPN: Discrete event systems.

Eq. 16 to distribution of signals, Eqs. 17 and 18 to accumulate tokens and Eqs. 19 and 20 to restart conditions should be evaluated after each marking of the net Mk+1to update the marking of LDPN and simulate cycled behavior of PLC. Marking of input places I is in function of discrete sensors states.

LDPN considers the following transition rules to dynamic behavior:

  • In initial conditions of LDPN, inhibitor arcs enable transitions and put token in its output places O and/or B in PN model with both inputs and outputs discrete. In AI places restart condition of data.

  • All output places (O and B) of the PN model are binary, only one can token.

  • All transitions enabled should be fired in one some evaluation. To PN model with both inputs and outputs discrete, transition fired T consume unique token WPT=1of each input place P of T and put to unique token WTP=1to each output place T of P. For PN model with some analog input place and output place discrete, the transition T should be fired when it satisfies the respective condition (if - then) and put to unique token in each output place T of P.

  • To update, marking should be applied Eqs. 1620.

3.3. Model of control lines both discrete inputs and outputs

Figure 11 shows the PN model of logic AND, if input places I1o,O3cyB2ohave a token, then L 1 transition is enabled. The L 1 firing puts a token at place O 1. When are updates the marking of input places, the Eq. (17) disables the L1 transition, avoiding a token more in output place O 1. By Eq. (19), the marking of place RC is in function of both marking input places and output place.

Figure 11.

PN model of logic AND.

Figure 12 shows the PN model of logic OR, if any input places I1c,O5oyB2ohave a token, then L 1 , L 2 or L 3 transition is enabled, respectively. If the transition enabled is fired, then a token is put at place O 1. When are updates the marking of input places, the Eq. (18) disables the L 1 , L 2 and L 3 transitions, avoiding a toke more in output place O 1. By Eq. (20), the marking of place RC is in function of both marking input places and output place.

Figure 12.

PN model of logic OR.

Figure 13 shows the PN model of logic AND-OR, output place can get token from L1 or L2 transitions, in function of marking of input places I1o,O3cyB2oor I1o,O3cyO7chave a token, respectively. The L 1 or L 2 firing puts a token at place O 1. When are updates the marking of input places, the Eqs. (17) and (18) disables the L 1 and L 2 transitions, avoiding a token more in output place O 1. The marking of place RC is in function of both marking input places of L 1 and L 2 transitions and output place O 1 based on Eqs. (19) and (20) to restart condition.

Figure 13.

PN model of logic AND–OR.

Figure 14 shows the PN model of logic auto-loop. In this model, it is necessary that L 1 transition to be enabled and fired set a token in the output place O 1, enabling the O1otransition, which consumes the token of O 1 and sets a token in the place O1o, enabling the L 2 and holding a token in O 1. The restart condition of the model auto-loop is in function of the Eqs. (19) and (20).

Figure 14.

PN model of logic auto-loop.

Figure 15 shows the PN model of logic interlocking. Both places O1 and O2 enable the O1cand O2ctransitions by the inhibitor arcs, placing a token in input places O1cand O2cof L 1 and L 2 transitions, respectively. If L 1 or L 2 transition is firing first disables the other transition by the inhibitor arc. The restart condition places RC 1 and RC 2 are in function of Eq. (19).

Figure 15.

PN model of logic interlocking.

3.4. Model of control lines with analog inputs and output discrete

Figure 16 shows the PN model of on-delay timer. The BT and PT are variables to determine base time and preset time, respectively. The marking of the place AI 2 is a data analog to store the sum ET=ET+BT. The marking of the place O 1 is in function of firing of the AI 2 transition, which depends on the condition ifI1=1&&ETPT. To restart condition of the places O 1 and AI 2 are in function of I1c.

Figure 16.

PN model of on-delay timer.

Figure 17 shows the PN model of logic off-delay timer. The place to restart condition RC and fire of RC 1 is putting a token in output place O 1 that is the initial condition of the structure PN. When the I1ctransition is fired put a token in place I1c, which enables AI 1 transition to allow the sum of time ET=ET+BT. The fire of AI 2 transition is in function of ifI1=0&&ETPT, if it is fired, then put a token in place AI 4, which enables AI 3 transition and consumes the token of place O 1.

Figure 17.

PN model of logic off-delay timer.

Figure 18 shows the PN model of logic up-counter and Figure 19 to PN model of logic down-counter. In both models, the marking of the place I1ois in function of MI1o=MI1t=0&&MI1t=0, which is to detect a positive transition in the marking, respectively. In place AI 1 are added the tokens (positive transition), ifCVPVthen AI 1 transition is enabled, and its fire put a token in place O 1. If the place RCI2ohas a token, then it is consumed the token of the place O1 and CV=0.

Figure 18.

PN model of logic up-counter.

Figure 19.

PN model of logic down-counter.

Figure 19 shows the PN model of logic down-counter, which has similar behavior to up-counter, just that if one token in place I1oconsume one token of place AI 1, ifCV0, then the fire of AI 1 transition puts a token in place O 1.

Figure 20 shows the PN model of logic of comparisons of two analog places. Enabling and firing of AI 1 is in function of ifV1=V2;ifV1<V2;ifV1>V2;according to the comparison. Similarly, the marking of place RC is in function of RCV1V2;RCV1V2;RCV1V2,respectively.

Figure 20.

PN model of logic of comparisons.

4. Example

Figure 21 shows the control algorithm in LD of run of three motors sequentially [14]. The Start and Stop signals are physical inputs of type pushbutton. The Motor_1, Motor_2 and Motor_3 coils are physical outputs. The IR1, IR2 and IR3 variables are bits of memory. The first control line is logic of auto-loop, if Start variable is equal to one, then, the IR1 coil is energized and so it is hold by the contact IR1. It is also energized the Motor_1 coil, and the timer T1 and T2 begin counting time. In T1, if ETPT, then, the IR2 and Motor_2 coils are energized. In T2, if ETPT, then, the IR3 and Motor_3 coils are energized. If Stop = 1, then, the IR1 coil is de-energized, and are restart conditions of the control algorithm. Table 2 shows the equivalence of signals in function of the definition LDPN.

Figure 21.

Run of three motors sequentially.

LDLDPN
StartI1
StopI2
Motor_1O1
Motor_2O2
Motor_3O3
IR1B1
IR2B2
IR3B3

Table 2.

Equivalence of signals of control algorithm in LDPN.

Figure 22 shows the LDPN to control algorithm of run of three motors sequentially. Restart conditions of the output places are in function of B1cby Eq. 19. The restarting condition of place B1 is in function of input places I1 and I2 by Eqs. 19 and 20. Restart condition places RC2 to RC6 are in function of the marking B1o, which are connected from B1c. For complex control algorithms implies a larger graphic LDPN, it is advisable to indicate the marking function of the places RC. Eq. 21 shows the incidence matrix of the PN model respectively, where the conditioning if-then of transitions for reasons of space, which are indicated on corresponding figures, is omitted.

Figure 22.

PN model of run of three motors sequentially.

The dynamic behavior of the PN model by run of three motors sequentially is described by the following marking. Fired the transitions with inhibitor arcs, initial marking M0 is:

E21

If place I 1 has token, which enable the I1otransition, its fire puts a token in the place I1o, which enabled the L 1 transition, its fire puts a token in the place B 1. In these conditions, by Eq. (16), the tokens in places of restarting conditions are consumed; the marking corresponding of LDPN is shown in Eq. (23).

E22

In these conditions, the B1otransition is enabled, its fire puts a token in four places B1o, this enables L 2 transition, its fire puts a new token in the place B1, it disables the fire of L 1 and L 2 transitions by Eqs. (17) and (18). Another place B1oenables L 3 transition; its fire puts a token in the place O 1. The others two places B1oenable AI 1 and AI 3 transition to add the base time, respectively. Eq. (24) shows these conditions of LDPN, besides the update marking.

E23

In these conditions, if ETPT, in both AI 2 and AI 4 transitions put a token in places O 2 and O 3, respectively. When place I2ohas a token enabling the RC 1 transition, its fire consumes a token in the place B1, restarting condition in LDPN.

5. Conclusions

There are two types of control lines for discrete event systems: those with discrete inputs and outputs, and those with analog inputs and discrete output. Twelve logics that were analyzed and converted into Petri network models.

For dynamic behavior of the PN model proposed, constraints and equations for marking places and firing transitions are indicated to consider the problems of mark accumulation and the restarting condition of the structure PN.

LDPN to discrete event systems allow to model control lines used in LD language, and consequently, control algorithms development in LD, supporting that these are safe and reliable.

Each PN model is independent and can be interconnected in function of the control logic, as well as, the number of PN model that is needed can be integrated.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution 3.0 License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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José Carlos Quezada Quezada, Ernesto Flores García, Joselito Medina Marín, Jorge Bautista López and Víctor Quezada Aguilar (September 19th 2018). Ladder Diagram Petri Nets: Discrete Event Systems, Petri Nets in Science and Engineering, Raul Campos-Rodriguez and Mildreth Alcaraz-Mejia, IntechOpen, DOI: 10.5772/intechopen.75753. Available from:

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