Along with rapid progress of optical fiber links in the physical layer of networks, optical processing in the control layer such as data links and internet layers is expected to realize photonic networks. Various kinds of architectures of optical routers and switches have been exploited. Optical buffering is one of the indispensable key technologies for avoiding packet collision in these network nodes.
Various optical buffering systems have been reported [1,2]. Most of them consist of optical fiber delay lines (FDLs). Although optical slow light can be a potential candidate to adjust short delay timing [3,4,5], FDLs are regarded to be most useful elements for packet buffering. Basically, two kinds of architectures of buffers with FDLs have been considered. One is a feedforward architecture, consisting of parallel FDLs that have different lengths corresponding to desired delay times. A combination of input and output buffered switch  and multistage FDL buffer  were reported as feedforward architectures. The other is an architecture consisting of feedback-looped FDLs. It potentially provides infinite delay time if waveform distortion caused by loss, noise, dispersion etc., is managed to be compensated. However, the FDLs can provide only a restricted function of a finite delay time as buffers because the optical packet cannot be read out during the propagation in the FDLs.
In most of the proposed architectures, electrical processing for scheduling and management has been employed [8-12]. Although flexible control including quality of service (QoS) can be realized using such a control method, simple autonomous control is preferable for simple and low-power consumption buffering.
We have proposed an autonomous first-in-first-out (FIFO) buffer management system using all-optical sensing of packets . Each of FDLs in the reported system stores a single packet. In this chapter, we describe architecture and operation of the buffering system. The buffering performances such as packet loss rate (PLR) and delay time are evaluated by numerical simulation.
2. Proposed Buffering System
2.1. Architecture of the Buffering System
The proposed buffering system consists of
The structure of a buffering module is also shown in inset of Fig. 1. It consists of a bit extractor, a controller, and an FDL buffer. The bit extractor creates trigger signal by detecting the first bit and the last bit of incoming packets. The first and last bits can be composed of specific coded bit patterns. Optical code-correlation processing can find the start and the end of the packet as the first and the last bits, respectively. The controller generates control signal autonomously by using the trigger signal. The FDL buffer stores and forwards packets by using the control signal.
2.2. Configuration of the Controller
Figure 2 shows the schematic diagram of the controller composed of four components. Controller A creates timing clock C1 to be used to open the buffer for storing packets. Controller B creates ‘store’ signal which indicates the actually storing FDL in the buffer. Controller C creates another timing clock C2 to be used to forward the already stored packets. Controller D creates ‘forward’ signal and the buffering information to other modules which indicates whether the buffer is now forwarding packets or not.
Figure 3 shows the configuration of controller A. Timing clock C1 corresponds to the extracted first bit of incoming packets. The extracted last bit is not used in this case. However, it is reserved for future enhancement of the buffering system.
Figure 4 shows the configuration of controller B. It autonomously generates ‘store’ signals by processing C1 and C2. The number of ‘store’ signals is
Figure 5 shows the configuration of controller C. It autonomously generates C2 by processing C1, ‘store’ signal, buffering information signals from other modules, and ‘forward’ signal mentioned below. The operation of controller C is similar to the FDL buffer for packets. Therefore, we describe the detailed operation in the latter section about FDL buffer.
Figure 6 shows the configuration of controller D. It autonomously generates ‘forward’ signal by processing C2. The ‘forward’ signal keeps on-state for a period of
2.3. Configuration of the FDL Buffer
The FIFO buffer consists of
2.4. Operation Overview of Buffering
An example of timing chart for buffering process of a module is shown in Fig. 8.
We assume that there are initially no packets stored in the FDLs, and then five packets are arriving sequentially with random timing and variable lengths. The number of FDLs
When packet no.1 is incident, ‘store’ signal #1 turns on triggered by the first bit and C1. The state of the ‘store’ signal is kept for a period of
Although similar operation can be seen for following packets, packet no.5 is slightly different. The front part of it is discarded because all FDLs have already been occupied by other packets. When packet no.3 is forwarded, FDL #2 is open for storing. At the moment, the rear part of packet no.5 is stored into there. Note that the packet no.5 is therefore treated as a broken packet when it gets out from the buffer.
3. Computer Simulation
Two kinds of characteristics such as packet loss rate (PLR) and average delay time are investigated by computer simulation. We assume in the simulation that packets arrive randomly and have variable lengths from
3.1. Packet Loss Rate
The PLR is verified with changing the number of FDLs
Figure 9 shows the PLR as a function of the load at module #1 with the number of FDLs
Figure 10 shows the PLR as a function of the load at module #1 with the length of FDLs
Figure 11 shows the PLR as a function of the load at module #1 with the load at module #2 as a parameter. The number of modules is
Figure 12 shows the PLR as a function of the load at module #1 with the number of module
Figure 13 shows the breakdown of such numbers as input, output, discarded and broken packet in (a) module #1 and (b) module #2. Parameters are set to as follows; the number of modules is
3.2. Average Delay
Packets stored and forwarded through the buffer have been experienced a certain amount of delay determined mainly by the load and parameters
Figure 14 shows the average delay as a function of the load at module #1 with the number of FDLs
Figure 15 shows the average delay as a function of the load at module #1 with the length of each FDL
Figure 16 shows distribution and moving average indicated by dots and solid curves, respectively, of delay time as a function of packet arrival time to each module with loads as parameters. The load of the module #1 is changed between 0.3, 0.5, and 0.7. The load of the module #2 is set to 0.5. The number of modules is
The length of each FDL is
We have proposed an autonomous first-in-first-out buffer with capability of storing a single packet in each of FDLs. Characteristics of PLR and average delay have been investigated by numerical simulation. As a result, the PLR and the average delay have a trade-off relation at such parameters as number of FDL