Open access peer-reviewed chapter

Line Impedance Emulator: Modeling, Control Design, Simulation and Experimental Validation

By Marwa Ben Saïd-Romdhane, Sondes Skander-Mustapha and Ilhem Slama-Belkhodja

Submitted: August 7th 2019Reviewed: October 10th 2019Published: March 11th 2020

DOI: 10.5772/intechopen.90081

Downloaded: 43

Abstract

The variation of line impedance has always been a great concern for grid operators and industrial users. The problem is that the reliability and quality of the supplied power are influenced by this variation. Indeed, several standards and grid requirements fix strict rules and rigorous standards when connecting or disconnecting from the public grid. In this context, this chapter proposes a full study of a line impedance emulator, which includes the power design and the control. The line impedance emulator is useful for small scale laboratories that develop distributed energy generation. Developed line impedance emulator is based on a three-phase power converter. For these converters, different controls are applied, including proportional integral and resonant controllers. For the generation of voltage reference values that correspond to expected line impedance, two algorithms are studied, namely, trigonometric functions-based algorithm and voltage drop-based algorithm. The theoretical study is supported by simulation and experimental results.

Keywords

  • power quality
  • distributed energy generation
  • microgrid
  • line impedance emulation
  • resonant controller

1. Introduction

Nowadays, with the tremendous increase of distributed energy generation (DEG), the concept of power quality (PQ) has become a growing concern for grid operators around the world [1, 2, 3, 4]. Many research teams working on this topic are developing small or large-scale DEG laboratories (Figure 1) [3, 4, 5, 6, 7, 8, 9] as well as algorithms for critical situations is the grid emulator. This grid emulator is also used to confirm the compliance with standards and different grid codes [10, 11, 12, 13].

Figure 1.

Example of a microgrid including line impedance emulators.

This chapter covers one of the functionalities of the grid emulator, which is the line impedance emulation. Indeed, line impedance deviation can be caused by several circumstances, such as, a remote grid fault, or a connection disconnection of a large load in the distribution network [14].

The line impedance variation is able to considerably affect reactive power sharing between parallel loads [15, 16], and it can also induce operation instability in case of standalone microgrid [17, 19]. In addition, line impedance value has an influence on the quality of voltage and line current in the point of common coupling of the microgrid [19]. In another hand, tests introducing line impedance variation are used for the compliance with many relevant standards especially those dealing with anti-islanding.

This chapter explains in details the steps of the line impedance emulator design based on power converters. Regarding line impedance emulation algorithm, reference voltage values are deduced in view of the phase shift with the input AC grid voltage, according to the equipment under test (EUT) active and reactive power. Presented emulator guarantee flexible tests with decoupled variation range of impedance component.

This chapter first outlines modeling of line impedance emulator, followed by a description of the control methodology for the overall, simulation results and experimental validation are then developed.

2. Line impedance emulator presentation

The line impedance emulator is installed between the grid and the EUT and used for the emulation of variable line impedance. The structure of the studied line impedance emulator system is shown in Figure 2. It incorporates two power converters joined by dc-link capacitor: an EUT side converter (EsC) and a grid side converter (GsC). The GsC and the EsC are AC/DC and DC/AC converters, respectively. To mitigate switching harmonics, an LCL filter is employed at the output of the EsC. The EsC control aims to maintain the voltage through the LCL filter capacitor Vc(abc) equal to the programmed references. The GsC has the intention of regulating the system power factor (PF) and the voltage at the DC bus Vdc. As presented in Figure 2, the line impedance emulator output Vout(abc) is equal to Vc(abc), while its output Vin(abc) is considered comparable to the grid voltage Vg(abc).

Figure 2.

Power converter-based three-phase line impedance emulator.

The flowchart of the line impedance emulator process is given by Figure 3. The first step of this flowchart consists in initializing the different functions and the microcontroller peripherals such as the ADC, Timers and the General Purpose Input/Output (GPIO) as well as the analog-to-digital conversion of the measured voltages and currents. The next step is to control of the GsC. The objective of this control is voltage at the DC bus regulation. In parallel with these steps, the impedance emulation algorithm provides the capacitor voltage references Vc(a,b,c)* according to programmed impedance. Once Vdc is equal to its reference and the capacitor voltage references Vc(a,b,c)* are generated, the operator proceeds to the control of the EsC. The desired line impedance is consequently achieved.

Figure 3.

Line impedance emulator process flowchart.

Figure 4 summarizes the different steps of the line impedance emulator design. As mentioned, the first step consists in modeling the two power converters of the line impedance emulator giving the system equations and transfer functions. After that, the operator selects the appropriate control converters control in terms of dynamic response, THD value, steady state error and sensitivity to perturbation and parametric variation. In this chapter, the control of the line impedance emulator converters employed resonant controllers and PI regulators. This choice is due to their simple use (tuning parameters and implementation), while ensuring simultaneously acceptable dynamic response, THD value and steady state error. Then, based on the obtained system transfer functions, the control parameters are deduced. After that, the operator should select the appropriate line impedance emulator algorithm. In this chapter, two impedance emulator algorithms will be presented. The next step of the design methodology consists in simulating the whole system including the power converters, the control strategy and the line impedance emulation algorithm. When the simulation results verify the proper system operation, the control will be implemented on a digital board. The last step of the design methodology consists in the experimental validation of the line impedance emulator.

Figure 4.

Methodology of the design of a line impedance emulator.

3. Line impedance emulator modeling

The GsC power circuit single phase representation is depicted on Figure 5, where Lg denotes the grid impedance. According to this figure, the GsC electric equation in the abc reference frame is given by Eq. (1).

Figure 5.

GsC power circuit.

Ui=VgLgdigdtE1

The EsC power circuit single phase representation is given by Figure 6. Based on this Figure, the equations related to the EsC are given by Eq. (2), Eq. (3), Eq. (4) and Eq. (5). The obtained single phase simplified block diagram of the LCL-EsC is depicted on Figure 7.

Figure 6.

EsC power circuit single phase representation.

Figure 7.

LCL-EsC simplified block diagram.

i1=ViVcsL1E2
i1=i2+icE3
Vc=icsCfE4
i2=VcVEsL2E5

4. Line impedance emulation control

4.1 Grid side converter control

Figure 8 shows the GsC control. It incorporates two control loops. The internal loop controls in the abc reference frame the grid currents ig(abc) and it is based on resonant controller. The external loop regulates, via a PI regulator, the voltage at the DC bus Vdc and provides grid current reference on d axis igd*. The grid current reference on the q axis igq* is selected to have the desired PF. For the abc grid current reference components ig(abc)*, they are obtained via the application of Park transformation to igd* and igq*. In the following, the tuning of the PI and the resonant controller parameters will be detailed.

Figure 8.

Block diagram of GsC control.

4.1.1 Tuning of the PI regulator of the voltage at the DC bus

Based on Figure 9, the current idc at the output of the GsC is expressed as in Eq. (6). By applying the Laplace transform to Eq. (6), Eq. (7) is obtained.

Figure 9.

DC bus voltage regulation loop simplified block diagram.

idc=ic+is=CdVdcdt+isE6
Vdc=1CsidcisE7

Since the current idc is instantaneously equal to ±ig and the current regulation loop time constant is insignificant compared to the one of the DC bus voltage regulation loop, Figure 9 gives simplified DC bus voltage regulation loop block diagram.

The transfer function of the PI regulator is given by Eq. (8). Based on this equation and neglecting the load current is, the closed-loop transfer function of the Vdc control is given by Eq. (9).

Gcs=idcΔVdc=Kpdc+KidcsE8
VdcVdc=KpdcCs+KidcCs2+KpdcCs+KidcC=KpdcCs+KidcCs2+2ξcωncs+ωnc2E9

The transfer function of Eq. (9) is a second-order system whose denominator can be written in the canonical form of a second-order system given by the right-hand side of Eq. (9). By identifying the terms of Eq. (9), the obtained transfer function is characterized by a damping ratio ξc and a natural frequency of oscillation ωnc that satisfy Eq. (10) and Eq. (11).

2ξcωnc=KpdcCE10
ωnc2=KidcCE11

Then, the form and the dynamics of the response of the DC bus voltage Vdc are imposed by setting the natural frequency of the oscillations ωnc and a damping coefficient ξc. Thus, the gains Kpdc and Kidc can be obtained based on equations Eq. (12) and Eq. (13).

Kpdc=2CξcωncE12
Kpdc=Cωnc2E13

4.1.2 Tuning of the resonant controller of the grid side current

The use of the PWM makes it possible to have a fundamental of the voltage Ui equal to its reference Ui*. Thus, based on Eq. (1), we obtain the simplified single-phase block diagram the grid side regulation loop given by Figure 10.

Figure 10.

Grid current regulation loop simplified block diagram.

Considering Figure 10, the closed-loop system transfer function (Tcig) is given by Eq. (14).

Tcigs=igsigsigs=Kpigs2+Kiigs+Kpigω02Lgs3+Kpigs2+Lgω02+Kiigs+Kpigω02E14

For the synthesis of the resonant controller parameters, we consider the pole placement method and more precisely the Naslin criterion [20, 21]. The n order polynomial of this criterion is expressed by Eq. (15).

PNaslins=n01++s2τ2α+s3τ3α3+..+snτnαnn1/2E15

From Eq. (14), we deduce the system characteristic polynomial given by Eq. (16).

Pigs=Lgs3+Kpigs2+Kiig+Lgω02s+Kpigω02E16

The identification between the system characteristic polynomial Pig and the second order Naslin polynomial makes it possible the deduction of resonant controller parameters Kpig, et Kiig as shown in Eq. (17) and Eq. (18).

Kpig=Lgα2τE17
Kiig=Lgα3τ2ω02=Lgα21ω02E18

4.2 EUT side converter control

The control based on resonant controller for the EsC is depicted on Figure 11. This control includes an external and an internal loops. The external one controls the voltages through the filter capacitor Vc(a,b,c). The internal one controls the inverter side current i1(a,b,c) and generates then the inverter voltages references Vi(a,b,c). For the external loop, a resonant controller is adopted. For the internal loop, the resonant controller is replaced by a constant gain (G) in order to ensure a faster loop than the external one. In the following, the tuning of the resonant controller parameters will be detailed and discussed in order to ensure good control performances.

Figure 11.

Block diagram of the EsC control.

4.2.1 Tuning of the resonant controller of the voltage through the LCL filter capacitor

For reasons of simplification, it is assumed that the internal loop of the current is faster than the external loop of the voltage. Thus, we can approximate it equal to the unity by associating the PWM function. Consequently, the block diagram of the voltage regulation loop is given by Figure 12.

Figure 12.

Voltage regulation loop simplified block diagram.

Hence, the closed loop system transfer function (Tc) is given by Eq. (19).

Tcs=VcVc=a2cs2+a1cs+a0cCfs3+a2cs2+Cfω02+a1cs+a0cE19

The method chosen for the computation of the resonant controller parameters is based on the generalized stability criterion [22]. In this case, the n order polynomial is expressed as in Eq. (20).

PGSCs=λs+ri=1ns+r+jωis+rjωiλrωiinNE20

On the other hand, based on Eq. (19), the system characteristic polynomial Pc is given by Eq. (21).

Pcs=Cfs3+a2cs2+Cfω02+a1cs+a0cE21

The identification of Pc and second order generalized stability criterion polynomial allows the deduction of the resonant controller parameters as shown in Eq. (22).

a2c=3rcλca1c=λc3rc2+ωi2Cfω02a0c=λcrc3+rcωi2Avecλc=CfE22

4.2.2 Tuning of the gain of the current i1

The simplified internal current regulation loop block diagram is given by Figure 13.

Figure 13.

Current regulation loop simplified block diagram.

Hence, the transfer function of the closed-loop system Ti1(s) is given by Eq. (23).

Ti1s=i1si1s=1L1Gs+1=11+τcswhereτc=L1GE23

G is chosen so that the real part of the inverse of the closed-loop time constant (1/τc) is greater than the stability margin chosen for the synthesis of the voltage external loop in order to ensure that the internal loop is faster than the external one.

5. Line impedance emulation algorithms

In this section, two methods of the line impedance emulator algorithm synthesis are presented: the trigonometric functions-based algorithm and the voltage drop-based algorithm.

5.1 Trigonometric functions-based algorithm

The impedance emulation conception is based on the phasor diagram depicted on Figure 14 According to this Figure, the apparent power S is expressed as in Eq. (24).

Figure 14.

Line impedance and phasor diagram.

S=VgI=VgVgVcZ=Vg2ZeVgVcZejθ+δE24

According to Figure 14, the reactive power Q and active power P are given by Eqs. (25) and (26), respectively. These equations allow the deduction of tanδ and the voltage magnitude Vout given, respectively, by Eqs. (27) and (28). On the other hand, the Q and P can be also written as a function of αβ output current and voltage components as shown in Eqs. (29) and (30), respectively.

Q=VgR2+X2RVcsinδ+XVgVccosδE25
P=VgR2+X2RVgVccosδ+XVcsinδE26
tanδ=PXQRVg2PX+QRE27
Vc=PXQRVgsinδE28
Q=32Vi2α+Vi2βE29
P=32Vi2α+Vi2βE30

Figure 15 shows the trigonometric-based line impedance emulation algorithm. The first step consists in measuring the grid voltage Vg(a,b,c) and computing its RMS value. From the obtained value, we compute the phase shifting δ relatively to the grid voltage. After that, the emulated impedance is computed based on the previous equations.

Figure 15.

Line impedance emulator algorithm-based trigonometric functions.

5.2 Voltage drop-based algorithm

This algorithm is based on a voltage drop Vv that matches with the emulated line impedance Z as shown in Figure 16 This voltage is a function of programmed inductance and resistance variations as presented in Eq. (31). The voltage drop-based line impedance emulator algorithm is presented in Figure 17.

Figure 16.

Voltage drop line impedance emulator principle.

Figure 17.

Reference voltage according to fixed line impedance.

Vv=Zi2=R+jXi2

6. Simulation and discussion

Simulation tests were performed under PSIM software. The proposed control was applied to a 20kVA line impedance emulator. Table 1 gives the line impedance emulator parameters. In Figure 18 is presented the Vdc response to a step reference of 100 V. Based on this result, the steady state error of the Vdc voltage becomes null in the steady state, which prove that this voltage is well regulated. Figure 19 shows that the voltage Vc(abc) is well regulated in both transient and steady state operation even reference magnitude change at 0.9 s. To show the voltage drop-based line impedance emulation algorithm performances, a control scenario is presented in Figure 20. This scenario consists in imposing in the interval [0, 1 s] equivalent real impedance in series with L2 and in the interval [1 s, 1.5 s] the line impedance emulator is activated. Figure 21 shows results for a line impedance Z characterized by X = 1.5 Ω and R = 1 Ω in case of real and emulated impedance. As shown in this figure, the same current value is generated for real and programmed line impedances.

DescriptionSymbolValueUnit
Nominal voltage line-lineVg400V
GsC nominal powerSGsCnom20kVA
EsC nominal powerSEsCnom20kVA
LCL filterConverter side inductorL12mH
EUT side filter inductorL22mH
CapacitorCf30μF
Switching frequencyfs10kHz

Table 1.

Line impedance emulator parameters.

Figure 18.

Vdc response to a step reference of 100 V.

Figure 19.

Line impedance emulator output in case of voltage reference magnitude change.

Figure 20.

Simulation control scenario.

Figure 21.

System output for real and programmed impedance for X = 1.5 Ω and R = 1 Ω.

7. Experimental validation

Figures 22 and 23 show the experimental prototype and the test bench for the line impedance emulator. It includes (1) an auto transformer used in order to vary the voltage peak magnitude; (2) an L filter (composed of three inductors (20 mH/20A) with 0.3 Ω internal resistors; (3) a 20 kVA AC/DC converter (GsC); (4) a dc-link capacitor (1100 μF/800 V); (5) a 20 kVA DC/AC converter (EsC); (6) an LCL filter (composed of three inductors (2 mH/10 A) with 0.1 Ω internal resistors, three capacitors (4 μF/400 V) and three inductors (2 mH/10A) with 0.1 Ω internal resistors); (7) a measurement board (LEM LA55 and LEM LV25 for currents and voltage measuring, respectively); and (8) the STM32F4-Discovery digital solution. It is worth noting here that two STM32F4-Discovery cards were used in the experimental test bench; the first one is dedicated to the GsC control and the second one is dedicated to the EsC control.

Figure 22.

Experimental prototype.

Figure 23.

Experimental test bench.

For both GsC and EsC controls, the switching frequency was fixed equal to 10 kHz. For experimental tests, the switching frequency is equal to 10 kHz, the voltage at the DC bus Vdc is initially charged at 55 V. Figure 24 presents the voltage at the DC bus Vdc response. As shown is this figure, Vdc is well controlled during steady state operation. Figure 25 presents the response of the line impedance emulator output for a reference change from 20 to 10 V. This test shows that the EsC control ensures an acceptable dynamic response and it is well controlled at steady state. Figure 26 presents the line impedance emulator input and the output that matches with various values of line impedance.

Figure 24.

DC bus measured voltage and reference values.

Figure 25.

Emulator output voltage Vc(abc) for voltage reference change from 20 to 10 V.

Figure 26.

Line impedance emulator input Vina and output Vouta for different values of R and L.

8. Conclusion

In this chapter, line impedance emulator was studied. This equipment is used in small scale laboratories studying distributed energy generation. It ensures power tests with variable line impedance. Presented line impedance emulator is based on two power converters connected via a dc-link capacitor. Theoretical study is detailed and validated by simulation and experimental tests. The proposed study describes in detail the control design of each power converter. In addition, two variants of line impedance emulator algorithms were synthesized. To prove the efficiency of the presented study, a test with a real impedance and an emulated one was performed and obtained results show the similarity of system responses with both equipment.

Acknowledgments

This work was supported by the Tunisian Ministry of High Education and Research under Grant LSE-ENIT-LR 11ES15.

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Marwa Ben Saïd-Romdhane, Sondes Skander-Mustapha and Ilhem Slama-Belkhodja (March 11th 2020). Line Impedance Emulator: Modeling, Control Design, Simulation and Experimental Validation, Numerical Modeling and Computer Simulation, Dragan M. Cvetković and Gunvant A. Birajdar, IntechOpen, DOI: 10.5772/intechopen.90081. Available from:

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