Equivalent circuit components for 25 GHz EBG absorber.
First, the chapter presents a novel design of electromagnetic bandgap (EBG) absorber with the characteristics of broad bandwidth, low profile, and polarization‐independence to a normal incident electromagnetic wave. The absorber is composed of three consecutive octagon or decagon loops, and highly‐resistive frequency selective surface (FSS) layers. Second, based on the feature of the designed absorber unit, a broadband, metamaterial absorber‐bounded, wireless inter/intrachip (WIIC) communication channel is constructed at the center frequency of 60 GHz. Third, in order to validate the developed methodology used in WIIC analysis, a wired channel on a conventional PCB has been measured, simulated, and analyzed. Fourth, with the extracted S‐parameters of the WIIC system and wired PCB channel, the system impulse responses and transfer functions of the investigated channels have been further extracted, which are used for validation and BER analysis of the WIIC system. Finally, it has been shown that based on the derived BER results, the performance of the designed WIIC channel is close to that of an additive Gaussian white noise (AWGN) channel when the WIIC transceivers are built in with the functionalities of forward error control (FEC), channel estimation, and equalization.
- metamaterial EBG
- wireless inter/intra chip communication
- channel design
- bit error rate
As the dramatic development of high speed integrated circuits and the fast increment of operating frequency of computer systems, the dimensions of complementary metal‐oxide semiconductor (CMOS) transistors have reached at the nanoscale. The very large scale integrated circuits, interconnecting communication channels and devices, and I/O pins have been becoming extremely complex, highly dense, and compact by using multilayer and complicated routing PCB technologies . When the frequency of the computer system operation is greater than 20 GHz or higher, the signal integrity (SI) bottlenecks have been becoming increasingly protuberant, which are particularly resulted in signal reflection, crosstalk, trace loss and delay, parasitic resistance, inductance, and capacitance [2–4].
In order to resolve these serious SI issues, several methods have been recently investigated to improve the interconnection communication systems. For example, using a low‐resistivity conductor or a low dielectric constant material, as well as multilayer stacked structures, improves the interconnection communication [5, 6]. Meanwhile, various approaches are used to eliminate traditional trace interconnection issues that have been explored for improving SI systems, including optical interconnects, electromagnetic wave solution, and radio frequency wireless communication technologies [7–11].
This chapter presents an innovative wireless inter/intrachip (WIIC) communication channel, as shown in Figure 1, where the major concept of the WIIC communication is illustrated to distinguish the existing high‐density trace communication‐based PCB and the wireless communication version developed in the chapter.
The rationale and motivation of this research are mainly resulted from the following considerations:
The WIIC system can greatly reduce the cost of PCB boards as the number of PCB layers is reduced from 10 of layers to less than 5 layers.
The WIIC system can fully take the advantage of the advanced and well‐developed wireless and mobile communication systems.
The wireless interconnect channel will be more convenient and flexible for layout chip distribution and for computer architecture design without concerning about wiring and routing of complicated vias and traces.
There is no crosstalk, low distortion, dispersion, and time delay, although interferences between transceivers are unavoidable on this designed WIIC board.
The long cycle process in designing and testing PCB trace wiring and routing will be completely eliminated.
2. Broadband EBG absorber design
2.1. Configuration of EBG absorber
The unit cell of the firstly proposed metamaterial EBG absorber, which is designed at the center frequency of 25 GHz, is displayed in Figure 2. The absorber unit includes a resistive layer, a dielectric substrate layer, and a ground layer. The octagon‐shaped resistive layer consists of three consecutive loops of highly resistive frequency selective surface (FSS). The material of the three loops is tantalum nitride with the relative dielectric constant of εr = 1, the relative permeability of μr = 1, and the conductivity of σ = 7400 S/m. The board substrate is foam‐characterized with εrf = 1.05, μrf = 1, and the loss tangent of tan δ = 0.005. The ground is made from copper with a conductivity of σ = 5.8 × 107 S/m.
Similarly, the proposed 60 GHz absorber unit is built with the substrate of foam characterized by the dielectric constant . The dimensions of the absorber unit are about 4.2 × 4.2 × 1 mm . The absorber unit consists of three consecutive decagon loops in order to achieve a broadband frequency band centered at 60 GHz. The thickness of the resistive metal layer is 0.02 mm, the width of the loop traces is 0.08 mm, the edge‐to‐edge spacing is 0.08 mm, and the side lengths of three loops are 0.3245, 0.2503, and 0.2256 mm, respectively.
2.2. Broadband absorption performance
The absorber unit has been built into an HFSS (high frequency structure system) environment, as presented in Figure 3, where the boundary surfaces of the unit cell are curtailed with the HFSS built‐in master and slave boundary conditions (BCs) in addition to two Floquet port excitations placed at the top and bottom as a wave port. In this case, the setting of the absorber unit can be considered as an equivalent, periodic, infinitely large absorbing configuration. Electromagnetic plane waves are placed to be incident onto the top surface of the absorber unit in the normal direction polarized as a transverse electric (TE) or a transverse magnetic (TM) wave.
The absorptance A(f) is a measure of the absorber's EM wave power absorption, which is precisely given as
where S11 and S21 are the reflection and transmission coefficients estimated in the two‐port network system, respectively. Because the absorber is essentially shielded by the copper ground, the EM wave cannot penetrate the structure, i.e., S21 = 0.
As shown in Figure 4, it is found that the proposed design of the absorptance A(f) of the 25 GHz EBG absorber unit is about 90% or greater in the frequency band of 19.9–31.2 GHz. The relative bandwidth of the designed absorber unit is approximately 44% centered at the frequency of 25.6 GHz. The predicted A(f) has been verified by an FDTD (finite difference time domain) simulation, which shows a higher agreement between those developed from the FDTD and HFSS methods .
2.3. Equivalent circuit analysis
It is very often to develop an equivalent circuit model for evaluating the absorptance A(f) of an EBG absorber speedily and efficiently in electrical engineering research and electronic engineering practice. An equivalent circuit for the EBG absorber unit has been presented using a transmission‐line model as displayed in Figure 5, where Ci, Li, and Ri (i=1, 2, 3) are the capacitance, inductance, and resistance for the ith one of the three resistive loops (i=1, 2, 3), and Cij, Lij, and Rij (i, j =1, 2, 3, i≠j) are correspondingly the mutual capacitance and inductance as well as resistance between the ith and jth resistive loops.
By neglecting the fringing effect, the capacitance of the parallel‐plate capacitor is approximated as 
where l is the perimeter of the resistive loop, w is the width of the trace, and εr is the relative permittivity of the substrate. C1, C2, and C3 are approximately evaluated by this relation.
Subsequently, the self‐inductance of a microstrip etched on the substrate can be expressed as 
where the above relation is used for gauging L1, L2, and L3, respectively, for the equivalent circuit.
The resistance introduced by the transmission‐line conductors can be approximated by 
where t is the thickness of the resistive layer, σ is the conductivity of the resistive layer, and δ is the skin depth of the conductor at the specified frequency of f. The skin depth of the resistive layer in the frequency band of 10– 40 GHz is within the range of 0.0292–0.0585 mm. Because the skin depth is greater than the resistive layer thickness t, RL in Eq. (4) should be used to calculate the resistances of the three loops. As shown in Figure 5, Rg, the resistance of the ground layer is also evaluated by employing Eq. (4).
The mutual capacitances and inductances among the resistive loops of the EBG absorber unit are approximated by employing the following relations :
where Cij and Lij (i, j = 1, 2, 3) are evaluated using the above two relations. In this absorber design, due to the small gaps between any two neighboring loops, the resistances R12 and R23 are approximately equal to the characteristic impedance of air; while due to that Loop2 separates Loop1 and Loop3, and R13 is very small and simply neglected here.
Given the permittivity εd, permeability μd, and conductivity σd of the dielectric substrate, by using the relations for the loss tangent, propagation constant and characteristic impedance 
The characteristic impedance in the substrate can be written as 
where the permittivity and permeability of substrate εd' = ε0εr, μd = μ0μr2,d” = 0, and tanδ’ = 0.005. The ground‐equivalent resistance and inductance shown in Figure 5 are initially set as Rd = Re(ηd), and Ld = Im(ηd)/jω, which can be easily evaluated using Eq. (8) for contribution from the substrate.
The equivalent circuit model of the EBG absorber unit has been established in the ADS with the configuration of components, as shown in Figure 5. The values of these circuit components are finely tuned and optimized, and the achieved results are listed in Table 1. The absorptance A(f) simulated from the equivalent circuit model in ADS is compared to that arrived from the corresponding HFSS full wave field solver as shown in Figure 6. In the frequency band of 18–40 GHz, A(f) results obtained from ADS equivalent circuit and HFSS field approach remain a fairly good consistent.
|R1 (Ω)||C1 (pF)||L1 (nH)||R2 (Ω)||C2 (pF)||L2 (nH)|
|R3 (Ω)||C3 (pF)||L3 (nH)||R12 (Ω)||C12 (pF)||L12 (nH)|
|R23 (Ω)||C23 (pF)||L23 (nH)||R13 (Ω)||C13 (pF)||L13 (nH)|
|Rd (Ω)||Ld (nH)||Rg (Ω)|
Similarly, for the 60 GHz EBG absorber, an equivalent circuit of the designed absorber unit has also been developed as shown in Figure 7.
By using the transmission line model, the self and mutual inductances, capacitances, and resistances are derived and put into a schematic in an ADS window. The values of the components are tuned in ADS as listed in Table 2.
|R1 (Ω)||C1 (pF)||L1 (nH)||R2 (Ω)||C2 (pF)||L2 (nH)|
|R3 (Ω)||C3 (pF)||L3 (nH)||R12 (Ω)||C12 (pF)||L12 (nH)|
|R23 (Ω)||C23 (pF)||L23 (nH)||R13 (Ω)||C13 (pF)||L13 (nH)|
|Rd (Ω)||Ld (nH)||Rg (Ω)|
The absorptance of the designed decagon absorber obtained in HFSS and the one derived from the equivalent circuit simulated in ADS are displayed in Figure 8, where the absorption bandwidths for both cases are approximately 20 GHz. They are fairly consistent, except a frequency shift in the front and back edges of the band. It is apparent that for this designs both the central frequency (60 GHz) and the absolute bandwidth (50–70 GHz) are the highest among the recent metamaterial EBG absorbers [19–24].
3. Wireless WIIC channel design
3.1. Construction of broadband wireless channel
Based on the design of the metamaterial absorber, a metamaterial‐absorbing layer bounded WIIC channel has been further designed . In the designed channel, two layers of the metamaterial EBG absorbers are placed on the top and bottom of the PCB board. Also, three antennas are placed on the top layer of the channel to perform the transceivers of chips in the WIIC system. The transceivers are used to transmit and receive signals operating at a 60 GHz frequency band. The WIIC channel is modeled in HFSS as shown in Figure 9.
The WIIC channel is designed with the total dimensions of 60 × 80 × 5 mm, which has been equipped with total 249 and 252 (14 × 18) absorber units on the top and bottom layers, respectively. The substrate dielectric material is filled with Foam in the designed in the WIIC channel. Three microantennas are placed on the top layer, which are fed with the coaxial lines. The antennas are about 30 mm apart from each other.
The HFSS‐simulated S‐parameters for the wireless PCB channel and a comparable structure, parallel plate system, are shown in Figure 10. As seen from the figure, the 10 dB bandwidth with acceptable insertion loss approximately ranges from 50 to 70 GHz. The insertion loss between the two transceivers ranges approximately from 22 to 35 dB in the frequency band from 50 to 70 GHz. The return loss is about -13 dB at the central frequency, with a minimum frequency of -32.06 dB at 49.62 GHz. It is noticed that the S‐parameters for the corresponding parallel plates are also fluctuated to meet the bandwidth requirement, and the insertion loss is much lower in the frequency band of interest.
3.2. Numerical extraction of impulse responses and transfer functions
To characterize the WIIC channel and to simplify the channel performance analysis, the impulse response is then extracted in ADS. The schematic for impulse response extraction and the time domain waveform of the input unit impulse are, respectively, shown in Figure 11.
The generated unit impulse is numerically determined to satisfy its definition as follows:
where is the magnitude of the pulse, and are the total pulse widths at the pulse top and bottom, respectively.
To compare the wireless PCB channel analysis to the existing wired trace approach, a wired PCB channel with a number of vias, striplines, microstrip lines, through whole pins, and connectors has been analyzed and measured. A motherboard, which includes a CPU on the top layer, is shown in Figure 12. The dimensions of the motherboard are 508 × 218 × 2.54 mm. There are a total of 22 layers on this PCB board, including eight stripline layers, two microstrip line layers, 10 ground planes, and two power planes. The size of the boards is much larger than the simulated wireless WIIC PCB, because the wired PCB channels consist of hundreds of traces at different layers to reduce the crosstalk among these traces.
The highlighted part of the board to be studied consists of a 300‐mil microstrip, two vias, a 5.3‐inch stripline, a through whole pin, and a connector. The wired PCB channel is measured using both TDR (time domain reflectometry) and TDT (time domain transmission) signals. The S11 and S12 can be approximately generated from the measured TDR and TDT signals, respectively. The reason for why not directly measuring the S-Parameters using a Vector Network Analyzer (VNA) to extract the S-Parameters is primarily due to that the cost of the VNA capable for the desired high frequency band of 50-70 GHz is too expensive. It was unavailable when doing the measurement for the wired PCB channel. The TDR/TDT signals will be used for extraction of the impulse response and transfer function of the channel. The wired PCB channel schematic diagram is displayed in Figure 12. The S‐parameter models of via, through whole pin, microstrip and stripline simulated in HFSS, and the connector S‐parameters model provided by the vendor are cascaded in ADS to generate the overall S‐parameters and to obtain the simulated TDT/TDR for the wired PCB channel.
The extracted impulse responses of the WIIC channel, measured and simulated wired PCB channels are shown in Figure 13. It is clearly seen that the measured and simulated impulse responses match very well.
As the frequency response of a system can be easily generated in MATLAB by performing an FFT to the impulse response. The discrete frequencies and the sampled time points have to satisfy the following relation :
where Δt is the sampling time interval of the impulse response, and N is the total samples of the impulse response in the time domain.
The extracted system transfer functions for the measured and simulated wired and wireless PCB channels are shown in Figure 14. It is clearly seen that the transfer functions of the simulated and measured PCB channels are very consistent, and they are almost cutoff from 15 GHz. However, the proposed wireless WIIC PCB channel performs very well for the desired frequency band around the neighborhood of 60 GHz. In other words, with an identical input to the channels, the bandwidth of the wireless WIIC PCB channels will be much larger than that of the wired PCB channel. The transfer function for the wireless WIIC PCB channel with the absorbers is relatively flat in the frequency range of 45–65 GHz. It is also noticed that this bandwidth is not completely consistent with that of the insertion loss resulted from HFSS.
4. System and channel performance analysis
4.1. WIIC transceivers
In this chapter, various advanced wireless and mobile technologies are implemented in the proposed WIIC system, including the orthogonal frequency division multiplexing (OFDM), quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), and multiple input multiple output (MIMO). Herein, an ideal 4 × 4 antenna array with the four identical channels is assumed, which correspondingly will lead to the upper bond data rate of the system. As the result of employing the technologies of OFDM, MIMO, and QPSK/QAM, the data rate and spectrum utilization of the system are dramatically improved.
The WIIC system in this work also includes forward error control (FEC), and interference mitigation to diminish the error brought by the channel and interferences from the channel and other transmitters. In this system, FEC mainly includes cyclic redundancy check (CRC) and channel coding, and interference mitigation features the techniques of scrambling and interleaving. For the FEC scheme, the system employs 16‐bit CRC and 1/3 code rate tail‐biting convolution coding. The WIIC system employs cyclic prefix (CP) to deal with the timing problem, and OFDM‐UWB (ultra wide‐band) to achieve low power consumption. The system block diagram is shown in Figure 15.
4.2. OFDM symbol decoding
MIMO demapping, demodulation, descrambling, deinterleaving, and channel decoding are all equipped in the OFDM symbol decoding scheme in this WIIC system [26–28]. Demodulation is able to automatically diminish the mistakes brought by the noise from the channels, and channel decoding can correct some errors in the receiving signals. Correctly MIMO demapping, demodulation, descrambling, deinterleaving, and channel decoding will provide the receiver the correct output bits, which can be used for comparison with the transmitted signals, and can accurately calculate the system BER.
As the precoding matrices employed by MIMO are orthogonal matrices, correspondingly, the inverse matrices, in other words, the deprecoding matrices are simply that are used for transposed precoding matrices. Thus, the deprecoding procedure will be the received signal matrix multiplied by the correct transposed precoding matrix. Besides, after deprecoding, the delayer mapping is the inverse procedure of the layer mapping, which is a procedure for collection and rearrangement of deprecoded data.
The constellation improvement of the SDM brought by precoding is simulated in MATLAB. The constellation diagrams collected at the receiver of a system without precoding, and that with precoding are displayed in Figures 16 and 17, respectively. The simulation includes 2,048,000 bits, under the AWGN channel, with SNR 5 dB.
4.3. WIIC system performance analysis
In the system and channel performance analysis, four different channels are investigated in MATLAB, which are the additive white Gaussian noise (AWGN), Rayleigh, the designed WIIC, and the measured PCB channels. The relationships of bit error rate (BER) and signal‐to‐noise rate (SNR) with four different channels are shown in Figure 18. In each SNR condition, a random binary of 441,600,000 bit stream is input to these four different channels and the BER is obtained by acquiring the number of bits in which the input and output are different.
Herein, BERs are extracted by directly comparing the input and output, so that the results are more reliable than obtaining BER by calculation using CRC‐checking results. Besides, in the simulation 0 dB antenna gain is assumed, and without including any low‐noise amplifier (LNA), as the worst‐case analysis of the simulated channels. Also, AWGN and Rayleigh channels provide the best or worst case for wireless channels, which cannot validate the designed system, but can also be compared to the proposed WIIC and wired PCB channels.
As predicted in the previous analysis, the BER reaches to be less than 10-5 at SNR of 3, 3.4, and 5.4 dB for AWGN, WIIC, and Rayleigh channels, respectively. Also, when SNR is greater than 3.6, 3.4, and 5.6 dB, none of the single error bit is found in BER analysis, with AWGN, WIIC, and Rayleigh channels, respectively. In contrast, it is not surprising that the BER for the wired PCB channel is much higher than the other channels due to its cutoff in the frequency band of interest.
In this chapter, based on the design of an EBG absorber unit, a WIIC channel has been designed and validated in the WIIC system. Also, as a reference system, a wired PCB channel is measured, simulated, and analyzed for extracting its S‐parameters and system transfer functions. It is found that the wired PCB boards are no longer qualified for transmitting signals at a 60 GHz band for the case studied, while the designed WIIC channel works properly in this band. With the extracted WIIC S‐parameters, its impulse responses and the normalized transfer functions are obtained in ADS and MATLAB. The BER analysis shows that the performance of the proposed WIIC channel is close to a simple AWGN channel when the WIIC transceivers are characterized with channel coding, channel sounding, channel estimation, and channel equalization.