1. Introduction: what makes memristors attractive for neural networks?
The ability of the memristors to change its conductance i.e. behaves like a resistor, and yet be able to remain in that conductive state, be able to change the state based on a control voltage makes it resemble like a neuron. The spiking neurons in the brain respond to the stimuli in different ways. The continuous application of stimuli and the changing response of the neuron to this is related to learning. In the same way, by application of voltage pulses of certain amplitude and frequency can cause a change in conductance state, reflecting as changing the amplitude of the current outputs through a memristor [1, 2, 3]. The voltage pulse trains below a threshold voltage for a given conductance state produces a current signal output that follows the input voltages reflecting learning ability. As such this idea can be translated to emulate spiking neurons with memristors [4, 5].
Another major design use case for memristor is the crossbar arrangement of the memristors. The memristors are arranged in a crossbar architecture, with each memristor being able to be accessed with rows and columns. The memristors are programmed using the transistor switch control, or selector switch control often referred to as ITIM or 1S1M configuration [6, 7]. Multiple transistors are usually required in the practical control circuits and depending on the complexity of the task such as the need to access multiple conductance states, the design aspects become complicated . Nonetheless, a single crossbar can emulate a single dot product matrix computation that is required for weighted summation of inputs in a neural network layer. From a design perspective, at a higher level the simplification of multiply and accumulate operation is simplified, and it can reduce the design complexity.
The neuro-memristive system requires architectural level combinations of crossbars and memristor neurons, and be able to fabricate along with CMOS devices. Usually, sensors, control circuits and memories, would be required for the neural network to be scaled to a large network. The larger the network or deeper the number of layers in the neural network, the complexity of implementing increases. Large crossbar arrays suffer from the sneak path currents and non-idealities of the devices, which introduces errors in the dot-product computations, that propagate from one layer to another. While to some extent these errors can be compensated with learning algorithms, they do not fully compensate for the changes in real-time conditions. Online learning is possibly a way to compensate for real-time errors, however, online learning systems are not easy to realise for analog circuits and often consume a large amount of area on-chip and power. For digital implementations, in general, online learning circuits consume larger area and higher delays, than the crossbar based analog counterparts.
2. Main challenges
2.1 Modelling issues
Modelling realistic memristors devices is a challenging task . There have been arguments for and against the existence of “ideal” memristor devices, based on electrical, physical, chemical and philosophical arguments [9, 10]. From a neural circuit design perspective, the arguments on the existence of such idealistic devices are practically not relevant. The more important question for the circuit designer is the accurate modelling of the practical device that can be either used as a spiking neuron or can be used in a crossbar.
When the models can incorporate into a simulator, it is important that the models represent accurately the true behaviour of the device and also are fast in terms of computation . The ability for the models to be easily integrated into SPICE like simulators, that can enable simulations of millions of neurons are important for building neural networks . Currently, the simulations with memristor models are extremely slow for deep neural networks, and often require the use of scripting languages such as Python to get around this issue.
2.2 Lack of design tools
There is limited availability of physical design kits (PDK) for use in standard design tools such as provided by Cadence , Mentor Graphics , Silvaco  etc. The support for memristor PDK suitable for integration with CMOS is largely an open problem. The accuracy of the design files is not comparable with CMOS processes, and the variability data is not very well disclosed. The design tools that can accurately translate the realistic memristor devices are not very common and is an active topic of study.
2.3 Reliability issues of memristors
The memristor devices suffer from a range of reliability issues. Some of the main issues include:
Ageing – the devices when switched ON and OFF for a long period of time suffer from the loss of conductance state. This creates a major problem in analog dot product computations with crossbar architecture. Ageing has better tolerance to binary neural networks [15, 16].
Noise – the electrical and thermal noise can play with the changes in output response of the memristors, which can interact with the design of the neurons. The exact interplay of the device noise within different configurations of the network is largely an open question .
Variability – the variability of the conductance due to process and fabrication challenges can create design challenges for the crossbars. The neural network design has shown to be tolerant to large variations in conductance [18, 19, 20]. The signal integrity and electromagnetics issues related to packaging also need to be taken into account in this challenge.
2.4 Complexity issues for programming memristors
Programming the memristors requires applying a series of voltage pulses for a sustained period of time until the conductance of the memristor changes to the desired value. The state changes are based on the magnitude of the voltages applied. The issue with the realistic design is the voltage control across several memristors is not an easy task. The memristors in crossbar are prone to non-idealities and often faced with variable threshold voltages. This makes the design of the programing logic complex [21, 22]. The ability to program memristor devices in parallel with low cost on the power, and area on-chip, is a challenging program, especially if the design is for analog neural networks .
2.5 Architectural challenges
There are several types of neural networks. Many designs have multiple layers and they involve convolution layers that involve dendrite logic . This makes the architecture design complex for generalisation. While crossbar-based designs can be used for a large number of neural network architectures, optimising the design for hardware is a totally different problem [6, 25]. The architectural changes need to be aligned with the circuit design challenges, especially, when the design constraints are with chasing accuracy and system-level performance metrics. The architectural designs also need to take care of a wide range of generalisation issues including those related to hardware-software co-design, and system of chip solutions .
2.6 Scaling and 3D integration
Scaling the CMOS circuits, and improving the packing density of the memristors are not a well-studied problem. There have been several suggestions on using 3D technologies and using vertical devices for very-large-scale integration [26, 27]. The main challenge in this regard has been the variability of the devices that prevent the large-scale 3D integration of crossbar-based designs. There are yet not full-proof solutions to scaling up in density and scaling up in size. The best architecture level scale-up is the use of modular designs that make use of several small crossbars to create larger ones [28, 29]. However, these designs are yet to be fully tested in a realistic commercial application.
2.7 Neuron model
There are several types of neurons in the human brain [30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40]. The cognition is a result of interactions between varied types of neurons in the cortex. Most neural networks inspire from the cortical neural networks and often are oversimplifications of the biological networks. The exact form of how intelligence over a life-time of human are not very well understood to completely build an equivalent machine intelligence. At best what we have achieved today in neuro-chips is weak intelligence, being able to implement some specific functionality of the human brain, that too not in its entirety. The journey of hardware AI research is its very early stages, with a scalable design similar to the human brain practically limited by the chemistry of how neurons work. The organic nature of the brain offers several advantages over the silicon neuron. The electrical models are many, but they all tend to be bulky and complex when implemented in silicon. Having a functionally complex neuron with simplistic implementation complexity is a major challenge in the system design of memristive neural networks.
3. Discussions and future outlook
While these challenges exist, the practical use of neural networks build with crossbar and that using memristive spiking neurons are many. Several problems having a few sets of sensors such as in biomedical sensing applications only need smaller neural networks to make the sensor intelligent. Likewise, many time-series based prediction problems use one-dimensional data that again only need simple recurrent neural networks.
The practical implementation of large scale networks is required to match the neural network scale and size of the human brain [41, 42, 43, 44, 45, 46]. Packing billions of neurons into a single chip is a major challenge, that requires to match the energy benchmarks and complexity. Current circuit implementations fail to match up with the energy benchmarks of the human brain, mainly as the scaling of power supply on chips are practically limited by electrical design and device constraints. In addition to this, packaging and electromagnetic effects also play a major role in building systems with neural chips. The precision engineering of these chips for reliable use is important for long term acceptability in higher intelligence tasks. Further, the data processing with the neurochips can be prone to adversarial attacks, which means the system needs to be made secure using dedicated cryptographic coprocessors. Going further, it will be also important to see the applications of these neurochips in human-machine interfaces, and for building connected and collective intelligence solutions.
Ageing is a time-dependent process, where the conductance of the memristors changes over a period of time and use [15, 16, 47, 48, 49]. The more the memristors are used, i.e., writing and reading, the ability to keep the expected conductance levels diminishes. This is wearing out the phenomenon that the memristor devices face due to continuous electrical stress on the devices impacting the chemistry and physics of the device. Over a period of time, the multiple conductance states get combined, or disappeared, making the reliability of programming memristors challenging. This makes fine-tuning as an essential part of memristor programming and test stages. Any changes in the conductance values introduce undesirable errors in the output of the crossbar arrays, which is far from expected ideal behaviour. This is a serious issue when the multiple conductance states are extensively used for building analog neural networks with crossbar arrays. The conductance of the memristors is equated to weights in the analog neural network, and hence if a conductance state goes missing it makes the training more complicated. Additional, rules need to be framed to the pre-trained network models to further adjust the weight values to achieve convergence. Learning and self-tuning in this sense is an online process for analog neural networks with memristor crossbar arrays. Nonetheless, the advantages of the analog neural networks with crossbar outweigh the digital-only counterpart, for smart sensor integration and edge AI computing [50, 51, 52, 53, 54, 55, 56, 57, 58, 59].
When the noise gets added to the signals at input, in-network layers or outputs of the analog neural network, it introduces errors in the layers of the neural networks. The noise can originate in different ways, such as due to thermal effects, electromagnetic effects, or through external sources. Noise is typically seen as a problem in circuits, however, with neural networks this may have some advantages to offer, such as with avoiding overfitting during training. The role of noise in the human brain is immense and it plays some major role in the way intelligence and perception is shaped [60, 61].
There are several open challenges in neuro-memristive circuit design. The design challenges go from classical circuit analysis to computer-aided design issues. The major bottleneck with creating a billion-neuron chip is the limitations imposed at the device and at architecture levels. There are yet no practical tools that can help address all the design challenges in a systematic way. Unlike software tools, where debugging is a well-detailed topic of study, the neuro-memristive hardware design is not easy to debug due to a variety of non-idealities of crossbar and memristor devices. There have been several proofs of concepts of circuit designs and a growing body of literature on architectures that aim to address these very challenges. However, there is a long way to go before many of these designs can be put for commercial use on a large scale. The digital designs of neural networks are much more feasible than analog neural networks at this point in time. In the future, it is expected that analog neural networks will have a much more important role to play in making sensors smarter and make intelligent computing energy-efficient.