Open access peer-reviewed chapter

Numerical Simulation and Compact Modeling of Thin Film Transistors for Future Flexible Electronics

By Arun Dev Dhar Dwivedi, Sushil Kumar Jain, Rajeev Dhar Dwivedi and Shubham Dadhich

Submitted: July 4th 2019Reviewed: October 28th 2019Published: June 10th 2020

DOI: 10.5772/intechopen.90301

Downloaded: 58

Abstract

In this chapter, we present a finite element method (FEM)-based numerical device simulation of low-voltage DNTT-based organic thin film transistor (OTFT) by considering field-dependent mobility model and double-peak Gaussian density of states model. Device simulation model is able to reproduce output characteristics in linear and saturation region and transfer characteristics below and above threshold region. We also demonstrate an approach for compact modeling and compact model parameter extraction of organic thin film transistors (OTFTs) using universal organic TFT (UOTFT) model by comparing the compact modeling results with the experimental results. Results obtained from technology computer-aided design (TCAD) simulation and compact modeling are compared and contrasted with experimental results. Further we present simulations of voltage transfer characteristic (VTC) plot of polymer P-channel thin film transistor (PTFT)-based inverter to assess the compact model against simple logic circuit simulation using SmartSpice and Gateway.

Keywords

  • OTFTs
  • numerical simulation
  • compact modeling
  • flexible electronics

1. Introduction

The interest in organic thin film transistors (OTFTs) has increased significantly in the past few years and has been proven for various applications such as flexible low-cost displays [1], organic memory [2], key components of RFID [3] tags, low-end electronic products, and polymer circuits and sensors [4]. Flexible electronics is a new technology that builds electronic circuits by depositing electronic products on flexible substrates like plastics, paper, and even cloth. Compared with inorganic electronics, organic or flexible electronics have the various following advantages. First, it can be manufactured at a very low cost at low temperatures. Second, it is thin, lightweight, foldable, and bendable and has a strong light absorption, no crushing, mechanical flexibility, low energy consumption, and high emission efficiency. Third, the cost is lower due to cheaper materials and lower-cost deposition processes [5], and it is also used for large area applications. Actually a stack of organic semiconductors (OSC) and low-temperature polymer gate dielectrics and the rapid annealing process are suitable with high-throughput, low-cost printing manufacturing [6]. Researchers replaced semiconductors with organic materials such as DNTT [7], poly(3-octylthiophene) (P3OT), poly(3-hexylthiophene) (P3HT), and poly(3-alkylthiophene) layers, and dielectric layers are used to create complete flexibility. A bigger challenge is to enhance the real performance of organic devices so as to expand their usage in real-time commercial applications [8]. To enhance the speed of the device, a very great deal of the research efforts has been dedicated to increasing the mobility of organic materials by improving the deposition conditions [9]. In addition to mobility, other methods of improving OTFT performance include scaling the length of channel and changing the active layer thickness. The OTFT is usually fabricated in an inverted structure with gate at the bottom, and source and drain will be at the top. Gundlach et al. [10] show that the bottom contact structure has a strong dependence on the contact barrier and due to the different nature of the interface between the channel and the insulator, the device exhibits different electrical properties [11]. Recently, for p-type OSCs, very high mobility values of several tens of cm2 V−1 s−1 have been reported for polymers and small molecules indicating that OSC has great potential for improved performance through chemical structures and process optimization [12]. In addition to performance, deep understanding of instability issues of OTFTs and finding stable and reliable solutions for OTFT is therefore very important [13]. Since the systematic cost of experimental investigation is very high and it requires a lot of time also, technology computer-aided design (TCAD) simulation of semiconductor devices is becoming very important for investigating the design and electrical characteristics of the device prior to fabrication of the device. Organic semiconductor technology has emerged in the past 20 years. Depending on the model, these devices have been developed and studied over the past decade. Compared to the silicon industry, for which public model is clearly defined and commonly used to provide designers with a relatively good description of the process, organic transistors still lack to have complete device models that can fully describe their electrical characteristics. Therefore TCAD simulation and compact modeling of organic transistors become very important.

In this chapter we present 2D device simulation of low-voltage DNTT-based OTFT using Silvaco’s ATLAS 2D simulator which uses Poisson semiconductor device equation [14, 15, 16, 17, 18, 19, 20, 21, 22] continuity equation for charge carriers, drift diffusion transport model, and density of defect states model for simulation electrical characteristics of the device. Silvaco’s UTMOST IV model parameter extraction software is used to get compact model parameters using UOTFT model [23]. Also TCAD simulation results and compact modeling results were compared and contrasted with the experimentally measured results of the device. Compact model has been applied for logic circuit simulation, and voltage transfer characteristics of PTFT-based inverter circuit have been simulated using the compact model parameters extracted from UOTFT model. This chapter contains five sections. This section introduces the content of the paper. The device structure and simulation are described in Section 2. The compact modeling, model verification, and parameter extraction are explained in Section 3. The results and discussion are explained in Section 4. Finally, conclusions drawn are given in Section 5.

2. Simulation

2.1 Device structure and finite element-based numerical simulation

The OTFT is designed on the bottom-gate top-contact of a flexible PEN substrate. A gate dielectric composed of a 3.6-nm-thick aluminum oxide layer and a 1.7-nm-thick n-tetradecylphosphonic acid self-assembled monolayer (SAM) was used [24]. Next, an organic semiconductor layer having a thickness of 11 nm was placed on the AlOx/SAM gate dielectric. The AlOx/SAM gate dielectric (5.3 nm) is very small in thickness and has a large capacitance per unit area, so transistors and circuits can operate at a low voltage of about 3 V. The OTFT has a channel length of 200 μm and a channel width of 400 μm, Lov = 10 μm.

The energy band diagram of a metal insulator semiconductor (MIS) structure is given in Figure 1. Maximum valence band energy (EV) and minima of conduction band energy (EC) of the inorganic semiconductor are substantially similar between the HOMO and the LUMO of the organic semiconductor. Especially for DNTT, HOMO is approximately −5.19 eV, and LUMO is about −1.81 eV [7, 24]. This introduces a large enough 3.38 eV HOMO-LUMO energy gap, which is sufficient for transistor operation.

Figure 1.

Energy band diagram of a metal insulator semiconductor (MIS) structure.

To start the ATLAS simulation, we defined the physical structure and device dimensions, including the location of the electrical contacts. Figure 2 shows a cross-sectional view of the bottom-gate, top-contact DNTT-based OTFT.

Figure 2.

Schematic cross-sectional diagram of organic TFTs along with the chemical structure of SAM and organic semiconductor.

2.2 Device physical equation

We can calculate these charge carrier densities by solving basic device equations simultaneously including Poisson equation [14, 15, 16, 17, 18, 19, 20, 21, 22], electron and hole continuity equation, charge transfer equation, and defect density of states equation. The first three equations are the default equations that ATLAS uses to find the electrical behavior of the device.

The Poisson equation determines the electric field intensity in the given device based on the internal movement of the carriers and the distribution of the fixed charges given by Eq. (1):

.E=divΨ=ρxyE1

where is the permittivity of the region and ρ(x,y) is the charge density given by.

ρxy=qpxynxy+ND+xyNAxyE2

where p(x,y) is the hole density, n(x,y) is the electron density, ND+(x,y) is the ionization donor density, and NA (x,y) is the ionization acceptor density.

To account for the trapped charge, Poisson equations are modified by adding an additional term QT, representing trapped charge given in (A):

divεΨ=ρxy=qnxypxyND+xy+NAxyQTE3

where QT = q(N+tD + NtA), N+tD = density × FtD, and NtA = density × FtA. Here, N+tD and NtA are ionized density of donor-like trap and ionized density of acceptor-like traps, respectively, and FtD and FtA are probability of ionization of donor-like traps and acceptor-like traps, respectively.

Due to charge accumulation, a potential is generated, which affects the intensity of electric field distribution and current. The voltage applied to the gate electrode generates an electric field that attracts a few or majority carriers. In addition, for OTFTs, the voltage potential between the source and the drain establishes another electric field along the channel that drives the charge carriers and produces a current.

The continuity equation describes the dynamics of charge carrier distribution over time as given in Eqs. (4) and (5):

∂n∂t=1q.Jn+GnRnE4
∂p∂t=1q.Jp+GpRpE5

In these equations, q is the magnitude of the electronic charge, n is the electron carrier density, p is the hole carrier density, J is the corresponding current density, G is the corresponding charge generation rate, and R is the corresponding charge recombination rate. For organic/metal oxide semiconductor field-effect transistors (MOSFETs), there is no optical absorption, so the term is simplified and the properties of the material are described by the minority carrier recombination lifetime. Since MOSFETs are majority carrier devices, the characteristics of carrier generation and recombination are relatively unimportant. The physical properties of organic semiconductors depend on the generation and movement of polarons [25].

A third important set of equations for describing the device physics for the charge carrier is given by

Jp=qnμpEqDppE6
Jn=qnμnE+qDnnE7

It contains drift and diffusion parts. These equations determine the current density based on the carrier mobility (μ), the electric field (E), the carrier density (n, p), and the diffusion coefficient of the carrier (D). Diffusion coefficient operators are related to Einstein’s mobility relationship:

Dn=kTqμnE8
Dp=kTqμpE9

In summary, the ATLAS software solves Poisson equations, continuity equations, and current density equations [26, 27] at each node in a two-dimensional grid for a given device structure simultaneously with itself and is subject to boundary conditions (including those applied at the contacts). With the help of ATLAS, the electric field distribution and electron and hole current density are calculated at each node and terminal current at electrode.

2.3 Density of defect states model

The assumed total density (DOS), g(E), consists of four bands: two tail bands (analogous to acceptor-like conduction band and donor-like valence band) and two deep energy bands (one donor-like and the other acceptor-like); they are modeled using a Gaussian distribution [15, 16, 17, 18, 19, 20, 21, 22, 28]:

gE=gTAE+gTDE+gGAE+gGDEE10

Here, E is the trap energy, EC is the conduction band energy, EV is the valence band energy, and the subscripts (T, G, A, D) stand for tail, Gaussian (deep level), acceptor, and donor states, respectively:

gTAE=NTAexpEEcWTAE11
gTDE=NTDexpEvEWTDE12
gGAE=NGAexpEGAEWGA2E13
gGDE=NGDexpEEGDWGD2E14

For exponential tails, DOS is defined by its conduction and valence band edge intercept densities (NTA and NTD) and by its characteristic attenuation energy (WTD and WTA).

For Gaussian distribution, DOS is given by the total state density (NGD and NGA), its characteristic attenuation energy (WGD and WGA), and its peak energy distribution (EGD and EGA).

2.4 Trapped carrier density

The ionized densities of donor and acceptor states are given by Eqs. (14) and (15):

nT=nTD+nGDE15
pT=pTA+pGAE16

where pTA, pGA, nTD, and nGDare given below

pTA=EvEcgTAE.ftTAEnpdEE17
pGA=EvEcgGAE.ftGAEnpdEE18
nTD=EvEcgTDE.ftTDEnpdEE19
nGD=EvEcgGDE.ftGDEnpdEE20

ftGA(E,n,p) and ftTA(E,n,p) are the ionization probabilities for the Gaussian acceptor and tail DOS, while ftTD(E,n,p) and ftGD(E,n,p) are defined as the probability of occupation of a trap level at energy E for the Gaussian and tail acceptor, and donor states in steady state are given by following equations [24, 25, 26, 27]:

ftTAEnp=vnSIGTAE.n+vpSIGTAH.niexpEiEkTvnSIGTAEn+niexpEiEkT+vpSIGTAHp+niexpEiEkTE21
ftGAEnp=vnSIGGAE.n+vpSIGGAH.niexpEiEkTvnSIGGAEn+niexpEiEkT+vpSIGGAHp+niexpEiEkTE22
ftTDEnp=vpSIGTDH.p+vnSIGTDE.niexpEEikTvnSIGTDEn+niexpEEikT+vpSIGTDHp+niexpEiEkTE23
ftGDEnp=vpSIGGDH.p+vnSIGGDE.niexpEEikTvnSIGGDEn+niexpEEikT+vpSIGGDHp+niexpEiEkTE24

where vn is the thermal velocity of electron, vp is the thermal velocity of hole, and ni is intrinsic carrier concentration. SIGGAE and SIGTAE are the electron capture cross sections subject to the Gaussian states and main tail, respectively. SIGGAH and SIGTAH are hole trap cross sections of the Gaussian states and acceptor tail, respectively. SIGTDE, SIGGDE, SIGTDH, and SIGGDH are the equivalent for donor states [8].

2.5 Poole-Frenkel mobility model

Firstly, Miller et al. [29] described the rate of monophonic jumps for simulating hopping in inorganic semiconductors. Later, Vissenberg et al. [30] studied the dependency related to carrier transport on the energy distribution and the jump distance in amorphous transistors, which further helps to find the carrier mobility. The very popular Poole-Frenkel mobility model [31] is given by

μnPFE=μn0expDELTAEN.PFMOBkTneff+BETAN·PFMOBkTneffGAMMAN.PFMOBEE25
μpPFE=μp0expDELTAEP.PFMOBkTpeff+BETAP·PFMOBkTpeffGAMMAP.PFMOBEE26

where μpPFEand μnPFEare the Poole-Frenkel mobilities for holes and electrons, respectively; μn0and μp0are defined as the zero-field mobilities for electrons and holes, respectively; and E is the electric field.DELTAEN.PFMOBandDELTAEP.PFMOBare the activation energy at zero electric field for electrons and holes, respectively.BETAN.PFMOBis the electron Poole-Frenkel factor, andBETAP.PFMOBis the hole Poole-Frenkel factor. Tneff is the effective temperature for electrons, and Tpeff is the effective temperature for holes.

3. Compact modeling, model parameter extraction, and model verification

The technology and operation of organic thin film transistors (OTFTs) have various unique features that require a dedicated compact TFT model. The important features of OTFT include operation in carrier accumulation mode, exponential density of states, interface traps and space charge-limited carrier transport, nonlinear parasitic resistance, source and drain contacts without junction isolation, dependence of mobility on career concentration, electric field, and temperature. The universal organic TFT (UOTFT) model [23] is a modeling expression that extends the uniform charge control model (UCCM) previously used for a-Si and poly-Si TFTs [23, 32] to OTFTs and introduces a general expression of modeling for conductivity of channel of OTFTs [30, 33]. In this way, the UOTFT model is applicable to various OTFT device architectures, specifications of material, and manufacturing technologies.

3.1 Model features

UOTFT model depends on a general-purpose compact modeling approach [23, 32], which provides smooth interpolation of drain currents between linear and saturated operating regions including channel length modulation effects and also provides the unified expression of the gate-induced charge in the conductive channel which is valid in all operating states. This model also gives a unified charge-based mobility description, drain-source current, and gate-to-source and gate-to-drain capacitances.

3.2 Model description

The control equation for the UOTFT model for the n-channel OTFT case is described here. The p-channel condition can be obtained by direct change in voltage, charge polarity, and current.

The charge accumulation in channel per unit area at zero-channel potential (−Qacc)o is calculated by the help of the solution of the UCCM equation given by [34].

Qacco=Ci.VgseE27
Vgse=VOT.ln1+eu+11+ku+2ln1+eu+1E28
u=VgsVTTVOTE29
kx=184.4839x2+150.864E30
Ci=0EPSITINSE31

where Ci is the gate insulator capacitance per unit area, Vgse is the effective intrinsic gate-source voltage, Vgs is the gate-source voltage (intrinsic), VT is the temperature-dependent threshold voltage parameter, and VO is characteristic voltage (temperature-dependent); for carrier density of states including the influence of interface traps, 0is the vacuum permittivity, and EPSI and TINS are model parameters representing the relative permittivity and thickness of the gate insulator, respectively.

3.3 Effective channel mobility

For accurate modeling of OTFTs, we should consider the characteristic power-law dependence of mobility on carrier concentration. According to the results of percolation theory [30], effective channel mobility is expressed in the UOTFT model as

μC=MUACCT.Qacc0Ci.VACCGAMMATE32

MUACC, VACC, and GAMMA are model parameters. MUACC is a temperature-related parameter which defines effective channel mobility at the onset of strong accumulation of channel. This onset point is controlled by model parameter VACC. The power-law dependence of the mobility on carrier concentration is defined by the temperature-dependent model parameter GAMMA.

3.4 Intrinsic drain-source current

Drain-source current of intrinsic transistor due to charge carriers accumulated in the channel is defined by general interpolation expressions [23]:

Idsacc=Gch.VdseE33
Vdse=Vds1+Gch.VdsIsat1+LAMBDA.VdsMSAT1MSATE34

where Gch is the effective channel conductance in the linear region, Vdse is the effective intrinsic drain-source voltage, Vds is the intrinsic drain-source voltage, parameter LAMBDA defines the finite output conductance in the saturation region, and MSAT is the model parameter that provides a smooth transition between linear and saturated transistor operation. Isat is the ideal intrinsic drain-source saturation current, and the effective channel conductance in the linear region Gch is obtained in the following way:

GCh=Gch01+Gcho.RdsE35
Gch0=WeffLeff.μc.Qacc0E36
Rds=RDST1+VgseVRDSE37

where Gch0 is the intrinsic effective conductance of channel in the linear region and Rds is the nonlinear bias-dependent series resistance for intrinsic channel region defined by temperature-dependent model parameter RDS and the model parameter VRDS; on the other hand, Weff and Leff are effective channel widths and length, respectively.

The drain saturation current Isat is determined by the following formula:

Isat=Gch.VsatE38

where Vsat is the saturation voltage obtained as

Vsat=ASATTCiQacc0GAMMAT+2+CiVOTGAMMAT+1E39

where ASAT is the temperature-dependent model parameter.

The drain-source leakage current is obtained as

Idsleak=weffLeff{IOLT.expNSDL.VdsVth1.expNSGLVgsVth+SIGMAO.VdsE40

The IOL is a temperature-dependent leakage saturation current model parameter; NGSL and NDSL are non-ideal factors for gate and drain bias, respectively, and SIGMAO is a model parameter representing zero-bias drain-source conductivity:

Vth=kTqE41

where Vthis the thermal voltage at device operating temperature.

The total intrinsic drain-source current is

Ids=Idsacc+IdsleakE42

4. Results and discussion

4.1 Material parameters used for DNTT

The DNTT-based OTFT is designed in a bottom-gate, top-contact configuration. The designed structure has a channel length of 200 μm and a channel width of 400 μm with Lov = 10 μm as shown in Figure 2. For the simulation of DNTT-based OTFT structure, the following parameters [24] used are listed in Table 1.

Material simulation parametersValue
DNTT energy band gap (eV)3.38 eV
Occupied molecular orbital Of DNTT (highest)−5.19 eV
Occupied molecular orbital Of DNTT (lowest)−1.81 eV
Intrinsic p-type doping in DNTT1016 cm−3
Fixed interface charge concentration5 × 1016 cm−3
Work function of aluminum gate4.1 eV
Work function of Au contact5.0 eV
Semiconductor thickness of DNTT11 nm
Dielectric thickness5.3 nm

Table 1.

Simulation parameters of material of the OTFT [17].

4.2 Comparison of TCAD-based numerical simulation characteristics and compact model-based simulation characteristics with experimental characteristics

Figure 3 shows the transfer characteristics obtained for the TCAD-based numerical simulation, compact model-based simulation of DNTT-based organic thin film transistor, and the measured characteristic of DNTT-based OTFT [24]. The transfer characteristics are obtained by varying the gate-to-source voltage (VGS) from 0 to −3 V keeping drain voltage constant at −2 V. There is very good agreement between TCAD-based numerical simulation, compact model-based simulation of the transfer characteristics of OTFT, and experimental transfer characteristics of the fabricated device. Figure 4 shows the output characteristics obtained from the TCAD-based numerical simulation, compact model-based simulation of DNTT-based organic thin film transistor, and the measured output characteristics of DNTT-based OTFT [24]. Output characteristics are obtained by varying the drain-to-source voltage (VDS) from 0 to −3 V and keeping the gate-to-source voltage (VGS) constant at −1.5, −1.8, −2.1, −2.4, −2.7, and −3.0 V. The simulated output characteristic matched with the experimental output characteristic of the fabricated device.

Figure 3.

Comparisons of transfer characteristics of the measured data, the TCAD-simulated data, and the modeled data.

Figure 4.

Comparisons of output characteristics of the measured data, the TCAD-simulated data, and the modeled data.

4.3 Parameter extraction

Extracted OTFT model parameters for low-voltage DNTT-based OTFT using UOTFT model is given in Table 2. The extraction process starts with the collection of data for ID-VG and ID-VD characteristic and providing it in UTMOST IV database in .uds format. Further we performed simulation of ID-VD and ID-VG characteristic using UOTFT model and optimization of this characteristic using Levenberg–Marquardt optimization technique with respect to experimental data for extraction of model parameters.

Parameter nameSymbolUNITTypical values
The thickness of gate insulatorTINSm5.3 × 10−9
Relative dielectric permittivity of the insulator at gateEPSI3.37
Relative dielectric permittivity of the semiconductorEPS3.0
Zero-bias threshold voltageVTV−0.884542
Trap density states characteristic voltageVOV0.0314021
Characteristic effective accumulation channel mobilityMUACCcm2/Vs1.85
Characteristic voltage of the effective mobilityVACCV1.0
Output conductance parameterLAMBDA1/V0.0
Knee-shape parameterMSAT5.0
Saturation modulation parameterASAT1.52
Leakage saturation currentIOLA1 × 10−10
Contact resistanceRS + RDKilo Ohm116.892

Table 2.

Model parameters extracted for UOTFT model.

4.4 Simulation of logic circuit

For UOTFT model validity, simple logic circuit has been implemented and simulated based on p-type OTFTs only. The schematic in Figure 5 shows the simple inverter circuit used in the simulation of a load transistor with auxiliary gate voltage (V). The given inverter circuit works like a potential divider between the driver and the load OTFT. When the input voltage is lower than the threshold voltage (more positive than VT), the driver OTFT turns off. On the other side, when it is more than the threshold voltage (more negative than VT), the driver OTFT turns on. The operation of the inverter also depends on load TFT size relatively with the driver TFT. To assess whether the simulation correctly reproduces this dependence, the size of load OTFT and its gate voltage (V) remain at the same value, while the size and gate voltage of driver OTFT change. Figure 6 shows the voltage transfer characteristic (VTC) plot of the inverter circuit under consideration for W/L ratio of 10, 120 1140 of driver TFT. As W/L ratio of the driver OTFT increases, its impedance decreases, and the transition between high and low states becomes clearer.

Figure 5.

A circuit diagram of the inverter circuit used for assessing the simulation results.

Figure 6.

Voltage transfer characteristics of inverter circuit shown for different W/L ratios of driver OTFT.

5. Conclusion

We presented a finite element method (FEM)-based device simulation of low-voltage DNTT-based OTFT by considering field-dependent mobility model and double-peak Gaussian density of states model using device simulator ATLAS. We also presented the application of UOTFT model and parameter extraction method to organic TFTs. We can also conclude that numerical simulations, experiments, and compact modeling-based simulation characteristics demonstrate the same behavior as matched in Figure 3 and Figure 4. We simulated an OTFT based on DNTT and demonstrated the application of the UOTFT model to organic TFTs and also use experimental data from DNTT-based OTFTs to extract parameters for Silvaco’s general-purpose organic TFT compact model. The model has been verified against logic circuit simulation. It has been concluded that UOTFTs provide more accurate modeling of the simpler parameter extraction methods for various organic TFTs. The results show that the UOTFT model correctly simulates the behavior of the devices reported in this study and is expected to be used for more complex circuits based on organic thin film transistors.

Acknowledgments

The authors are thankful to SERB, DST, Government of India, for the financial support under Early Career Research Award (ECRA) for Project No. ECR/2017/000179.

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution 3.0 License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Arun Dev Dhar Dwivedi, Sushil Kumar Jain, Rajeev Dhar Dwivedi and Shubham Dadhich (June 10th 2020). Numerical Simulation and Compact Modeling of Thin Film Transistors for Future Flexible Electronics, Hybrid Nanomaterials - Flexible Electronics Materials, Rafael Vargas-Bernal, Peng He and Shuye Zhang, IntechOpen, DOI: 10.5772/intechopen.90301. Available from:

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