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Mathematics » "Fourier Transforms - High-tech Application and Current Trends", book edited by Goran S. Nikolic, Milorad D. Cakic and Dragan J. Cvetkovic, ISBN 978-953-51-2894-6, Print ISBN 978-953-51-2893-9, Published: February 8, 2017 under CC BY 3.0 license. © The Author(s).

Chapter 6

Application of Fourier Series Expansion to Electrical Power Conversion

By Irina Dolguntseva
DOI: 10.5772/66581

Article top

Overview

Half-bridge one phase two-level inverter leg.
Figure 1. Half-bridge one phase two-level inverter leg.
Carrier waveform: (a) saw-tooth leading edge; (b) saw-tooth trailing edge; (c) double edge.
Figure 2. Carrier waveform: (a) saw-tooth leading edge; (b) saw-tooth trailing edge; (c) double edge.
Contour plots for a sine modulated reference waveform and different carrier modulating waveform: (a) saw-tooth leading edge; (b) saw-tooth trailing edge; (c) double edge.
Figure 3. Contour plots for a sine modulated reference waveform and different carrier modulating waveform: (a) saw-tooth leading edge; (b) saw-tooth trailing edge; (c) double edge.
DCMLI circuit topologies: (a) three-level; (b) five-level.
Figure 4. DCMLI circuit topologies: (a) three-level; (b) five-level.
POD PWM scheme for a five-level inverter with the sinusoid reference waveform.
Figure 5. POD PWM scheme for a five-level inverter with the sinusoid reference waveform.
APOD PWM scheme for a five-level inverter with the sinusoid reference waveform.
Figure 6. APOD PWM scheme for a five-level inverter with the sinusoid reference waveform.
PD PWM scheme for a five-level inverter with the sinusoid reference waveform.
Figure 7. PD PWM scheme for a five-level inverter with the sinusoid reference waveform.
PD PWM scheme for a three-level diode-clamped inverter.
Figure 8. PD PWM scheme for a three-level diode-clamped inverter.
POD PWM scheme for a three-level diode-clamped inverter.
Figure 9. POD PWM scheme for a three-level diode-clamped inverter.
PD PWM scheme for a five-level diode-clamped inverter (here ϕ2=π−ϕ1 and ϕ1=cos−1(1/2M)).
Figure 10. PD PWM scheme for a five-level diode-clamped inverter (here ϕ2=π−ϕ1 and ϕ1=cos−1(1/2M)).
POD PWM scheme for a five-level diode-clamped inverter (here ϕ2=π−ϕ1 and ϕ1=cos−1(1/2M)).
Figure 11. POD PWM scheme for a five-level diode-clamped inverter (here ϕ2=π−ϕ1 and ϕ1=cos−1(1/2M)).
APOD PWM scheme for a five-level diode-clamped inverter (here ϕ2=π−ϕ1 and ϕ1=cos−1(1/2M)).
Figure 12. APOD PWM scheme for a five-level diode-clamped inverter (here ϕ2=π−ϕ1 and ϕ1=cos−1(1/2M)).
Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using NS POD/APOD PWM.
Figure 13. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using NS POD/APOD PWM.
Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using NS PD PWM.
Figure 14. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using NS PD PWM.
Theoretical harmonics spectrum of a five-level diode-clamped inverter modulated using NS POD PWM.
Figure 15. Theoretical harmonics spectrum of a five-level diode-clamped inverter modulated using NS POD PWM.
Theoretical harmonic spectrum of a five-level diode-clamped inverter modulated using NS APOD PWM.
Figure 16. Theoretical harmonic spectrum of a five-level diode-clamped inverter modulated using NS APOD PWM.
Theoretical harmonic spectrum of a five-level diode-clamped inverter modulated using NS PD PWM.
Figure 17. Theoretical harmonic spectrum of a five-level diode-clamped inverter modulated using NS PD PWM.
Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using SR POD PWM.
Figure 18. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using SR POD PWM.
Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using SR PD PWM.
Figure 19. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using SR PD PWM.
Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using AR POD PWM.
Figure 20. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using AR POD PWM.
Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using AR PD PWM.
Figure 21. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using AR PD PWM.
A single-phase H-bridge (full-bridge) inverter.
Figure 22. A single-phase H-bridge (full-bridge) inverter.
A five-level cascaded H-bridge inverter topology.
Figure 23. A five-level cascaded H-bridge inverter topology.
Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using NS PS PWM.
Figure 24. Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using NS PS PWM.
Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using NS PS PWM.
Figure 25. Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using NS PS PWM.
Theoretical harmonic spectrum of a single-phase cascaded H-bridge inverter modulated using NS PS PWM.
Figure 26. Theoretical harmonic spectrum of a single-phase cascaded H-bridge inverter modulated using NS PS PWM.
Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using SR PS PWM.
Figure 27. Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using SR PS PWM.
Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using SR PS PWM.
Figure 28. Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using SR PS PWM.
Theoretical harmonic spectrum of a single-phase cascaded H-bridge inverter modulated using SR PS PWM.
Figure 29. Theoretical harmonic spectrum of a single-phase cascaded H-bridge inverter modulated using SR PS PWM.
Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using AR PS PWM.
Figure 30. Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using AR PS PWM.
Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using AR PS PWM.
Figure 31. Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using AR PS PWM.
Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using AR PS PWM.
Figure 32. Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using AR PS PWM.

Application of Fourier Series Expansion to Electrical Power Conversion

Irina Dolguntseva
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Abstract

Many power electronic applications demand generation of voltage of a rather good sinusoidal waveform. In particular, dc-to-ac voltage conversion could be done by multilevel inverters (MLI). A number of various inverter topologies have been suggested so far: diode-clamped (DC) MLI, capacitor-clamped (CC) MLI, cascaded H-bridge (CHB) MLI, and others. Fourier series expansions have been used to investigate and to form a basis of different topologies comparison, to discover their advantages and disadvantages, and to determine their control. In this chapter, we discuss modulation strategies of DCMLI and CHBMLI, solve their harmonics spectra analytically, and compare them using harmonic distortion indices.

Keywords: Fourier series, multilevel inverters, pulse width modulation, harmonics, THD

1. Introduction

The term “power electronics” is used for a family of electrical circuits which convert electrical energy from one level of voltage/current/frequency to other using semiconductor-based switches. The switching process in power electronic converters is called modulation, and development of optimum modulation strategies has been the subject of research in power engineering during several past decades. Electrical power conversion has evolved as new topologies, switching devices, control, and modulation strategies have been proposed. Each group of power electronic converters has its own preferable modulation approach optimizing the circuit performance, addressing such issues as switching frequency, distortion, losses, and harmonics generation. Only voltage source inverters modulation will be discussed below.

Before turning to specific issues of modulation, one needs to establish a common basis to compare the modulation schemes. Different merits are used to evaluate a particular pulse width modulation (PWM) implementation: diminished harmonics [1], filtered distortion performance factors [2], and the root-mean-square (RMS) harmonic ripple current [3]. In this text, analytical solutions to PWM strategies are used to compare magnitude of various harmonic components. This approach has a number of advantages [4].

Firstly, the conventional method of determining harmonic components of a switched waveform using fast Fourier transform (FFT) of the waveform is sensitive to the time resolution of the simulation and periodicity of the overall waveform. Moreover, it ensures that intrinsic harmonic components of PWMs are not affected by such factors as simulation round off errors, dead time, switch ON-state voltages, DC bus ripple voltages, etc.

Secondly, PWM strategies can be compared at exactly the same phase leg switching frequency.

And thirdly, the first-order weighted total harmonic distortion (WTHD) is used for a quick comparison of PWMs since it has a physical meaning (the normalized current ripple expected into an inductive load when fed from the switched waveform) and often used performance indicator.

The rest of the paper is organized as follows. In Section 2, information on the double Fourier series expansions and necessary relations is given. Essentials on PWM are provided in Section 3. Different voltage inverter topologies and their analytical PWM solutions are presented in Section 4. Harmonic distortion factors of the introduced inverter topologies, different modulation schemes are compared in Section 5, and a summary on the chapter is given in Section 6.

2. Double Fourier series expansion

2.1. Double Fourier series decomposition for a double variable function

It is well known that a periodic two variable waveform f(x,y) can be expressed in the form

f(x,y)=A002+n=1[A0ncosny+B0nsinny]+m=1[Am0cosmx+Bm0sinmx]+m=1n=n0[Amncos(mx+ny)+Bmnsin(mx+ny)]
(1)

where the double Fourier series components can be found in a complex form:

Cmn=Amn+jBmn=12π2ππππf(x,y)ej(mx+ny)dxdy.
(2)

The first term in Eq. (1) is the DC offset that should be zero or negligibly small. The second summation term represents the baseband harmonics. The first baseband harmonic, n=1, is the fundamental harmonic whose magnitude defines the magnitude of the output waveform. Other baseband harmonics, n>1, represent low-frequency undesired fluctuations about the fundamental output and should preferably be eliminated with the modulation process. The third summation term in Eq. (1) corresponds to the carrier harmonics which are relatively high-frequency components. Finally, the last double summation term in Eq. (1) corresponds to groups of the sideband harmonics of order n located around the mth carrier harmonic component.

2.2. Jacobi-Anger expansion and Bessel functions relations

The magnitudes of harmonic components in Eq. (1) are to be determined for each PWM scheme for each particular combination of indexes m and n. The evaluations are based on Jacobi-Anger expansions

e±jξcosθ=J0(ξ)+2k=1j±kJk(ξ)coskθ=k=jkJk(ξ)ejkθ
(3)

and a number of Bessel function properties: Jn(ξ)=(1)nJn(ξ) and Jn(ξ)=(1)nJn(ξ), that particularly implies J0(ξ)=J0(ξ) [5].

2.3. Parseval’s theorem

Givenf(x) is a periodic function with the period T, it can be represented by its Fourier series f(x)=a0/2+n=1ancosnωt+bnsinnωt where ω=2π/T is the fundamental angular frequency. Then, on [T/2,T/2], the Parseval’s theorem assumes the form

1TT/2T/2f2(x)dx=a024+n=1an2+bn22.
(4)

3. Pulse width modulation

To introduce the concept of PWM, let us consider a basic configuration of one-phase two-level inverter leg shown in Figure 1. It consists of two switches, S1 and S2, and two diodes, D1 and D2. Switches S1 and S2 are operating alternately at high frequency to generate a quasiperiodic output voltage va(t), whose low-frequency components are intended to deliver a prescribed AC supply. When the switch S1 (S2) is ON, a positive voltage, +Vdc, (respectively, negative voltage, Vdc) is supplied to a load at the connection point a.

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Figure 1.

Half-bridge one phase two-level inverter leg.

The essential concept of a two-level pulse-width-modulated converter system is that a low-frequency target waveform is compared against a high-frequency carrier waveform, and the comparison result is used to control the state of a switched phase leg. In case of the inverter in Figure 1, the phase leg is switched to the upper DC rail when the target waveform is greater than the carrier waveform, otherwise to the lower DC rail. As a result, a sequence of pulses switching between the upper and the lower DC rails is generated, which contains the target waveform as the fundamental component but also a series of unwanted harmonics arising due to the switching process.

The most well-known analytical method of determining the harmonic components of a PWM switched phase leg was first developed by Bowes and Bullough [1], who adopted an analysis approach originally developed for communication systems by Bennet [6] and Black [7] to modulated converter systems.

The analysis is based on the existence of two time variables x(t)=ωct and y(t)=ω0t, where ω0 and ωc are the angular frequencies of the fundamental (target, sinusoid) low-frequency modulated waveform and the carrier high-frequency modulating waveform, ω0ωc.Variables x(t) and y(t) are considered to be independently periodic. If the ratio ωc/ω0 is integer, the generated pulse width trail will be periodic [4].

The problem of finding a PWM for the modulated periodic waveform f(t) can be solved by exploring a unit cell which identifies contours within which f(t) remains constant for cyclic variations of x(t) and y(t) and is equal to the phase leg output voltage. Thus, a three-dimensional (3D) unit cell is a plot of two time variables function with z assuming values of f(x,y) where x and y vary from π to π. Contours of f(x,y) within the unit cell depend on a particular PWM strategy which will be discussed below.

3.1. Carrier-based PWM schemes

3.1.1. Carrier waveforms and unit cells

Since the target waveform is usually a sinusoid, PWM schemes can be categorized based on the carrier waveform: saw-tooth leading edge (Figure 2a), saw-tooth trailing edge (Figure 2b), and double edge (Figure 2c).

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Figure 2.

Carrier waveform: (a) saw-tooth leading edge; (b) saw-tooth trailing edge; (c) double edge.

Let the modulated waveform of a phase be given vaid=Mcosy, where M is the modulation index, 0<M<1. For the one-phase two-level inverter leg shown in Figure 1, unit cells with contour plots for each carrier waveform modulation are presented in Figure 3. The output of the modulated waveform assumes either +Vdc or Vdc, and the regions of the constant output are bounded by reference waveforms Ω(y)=±πMcosy. For saw-tooth modulations, one of switching time instances (within a period of the carrier waveform) is independent of the reference waveform resulting in only one side of the contour plot to be sinusoid. The double-edge PWM both sides of the switched output are modulated providing better harmonic performance unlike saw-tooth modulations [4]. Hereinafter, only double-edge modulation is considered.

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Figure 3.

Contour plots for a sine modulated reference waveform and different carrier modulating waveform: (a) saw-tooth leading edge; (b) saw-tooth trailing edge; (c) double edge.

To determine the harmonics content and the output waveform of a particular PWM, the double Fourier series coefficients Cmn (or, equivalently, Amn and Bmn) are to be found using Eq. (2). To solve the problem, the periodic function f(x,y) is to be integrated over the unit cell of the PWM scheme.

3.1.2. PWM sampling schemes

Based on the choice of switching time instances, PWM schemes can be divided into: naturally sampled (NS), symmetrically regularly sampled (SR), and asymmetrically regularly sampled (AR) PWMs.

3.1.2.1. Naturally sampled PWM

For NS PWM scheme, switching occurs at time instances corresponding to intersection of the carrier and target waveforms. Switching time instances can also be determined as the intersection between the reference waveform and the solution trajectory y=(ω0/ωc)x. For example, switching time instances for the NS double-edge modulation of the one-phase two-level inverter leg in Figure 1 are defined from its unit cell in Figure 3c such that f(x,y) changes

  • ­ from Vdc to Vdc when x=πMcosy,

  • ­ from Vdc to Vdc when x=πMcosy.

3.1.2.2. Symmetrically regularly sampled PWM

Switching instances for SR PWM can be determined by the intersection between the sampled sinusoid waveform and the solution trajectory line y=y+(ω0/ωc)x. The same switching instances can be determined as the intersection between the continuous sinusoid waveform and a staircase variable y which has a constant value within each carrier interval [4]. In general, the value of y within each carrier interval can be expressed as

y=ω0ωc2pπ,p=0,1,2,
(5)

where p represents the pth carrier interval within a fundamental cycle. The staircase variable y in terms of continuous variables x and y is given by

y=yω0ωc(x2pπ),p=0,1,2,.
(6)

The double Fourier series coefficients for the case of SR PWM with a triangle carrier can be found analogously to NS PWM with variable y substituted by variable y found from Eq. (6).

Considering the previous example with the one-phase two-level inverter leg shown in Figure 1, switching time instances for the SR double-edge modulation are defined such that f(x,y) changes

  • ­ from Vdc to Vdc when x=πMcosy,

  • ­ from Vdc to Vdc when x=πMcosy.

3.1.2.3. Asymmetrically regularly sampled PWM

Switching time instances for AR PWM are determined similarly to SR PWM. Unlike SR PWM, switching occurs twice within each carrier interval for AR PWM. The switching time instances can be determined as the intersection between the continuous sinusoid waveform and two staircase variables

yi=ω0ωc(2pπ+(1)iπ2),i=1,2,
(7)

which can be expressed in terms of continuous variables x and y as

yi=yω0ωc(x2pπ(1)iπ2),i=1,2.
(8)

To write the double Fourier series integral for AR PWM, the switched waveform in each carrier interval must be split into two sections for analysis, and with the results added by superposition, the first section (i=1) has modulated “rising” edge in the first half carrier interval and a “falling” edge in the center of the carrier interval. The second section (i=2) has a modulated “rising” edge in the center of the carrier interval and “falling” edge in the second half carrier interval. Mathematically, this behavior can be expressed as a sum of two functions, f1(x,y) and f2(x,y), representing “rising” and “falling” edges of the double-edge carrier waveform f(x,y)=f1(x,y)+f2(x,y).

In the previous example with the one-phase two-level inverter leg (Figure 1), functions f1(x,y) and f2(x,y) are defined as follows:

  • ­ f1(x,y) steps from Vdc to Vdc at x=x(y1)+2pπ and from Vdc to Vdc at x=2pπ;

  • ­ f2(x,y) steps from Vdc to Vdc at x=2pπ and from Vdc to Vdc at x=x(y2)+2pπ.

4. PWM for multilevel inverters

In this section, the following MLI topologies are presented: diode-clamped (DC) MLI, cascade H-bridge (CHB) MLI, and capacitor-clamped (CC) MLI. The three-level diode-clamped inverter, which is also called the neutral-point-clamped inverter, was initially introduced by Nabae et al. [8] in 1981. Thereafter, diode-clamped, cascade H-bridge, and flying capacitor MLIs with higher number of DC voltage levels have been developed [911].

4.1. Diode-clamped MLI

4.1.1. DCMLI circuit topology

A three-level diode-clamped inverter is shown in Figure 4a. In this circuit, the DC bus voltage is split into three levels by two series-connected bulk capacitors, C1 and C2. The middle point of the two capacitors n can be defined as a neutral point. The inverter has two complementary switch pairs: (S1,S3) and (S2,S4); the complementary switches cannot be turned on simultaneously. The output voltage va has three states: Vdc/2, 0, and Vdc/2. For voltage level Vdc/2, switches S1 and S2 should be turned on; for Vdc/2, switches S3 and S4 should be turned on; and for the 0 level, switches S2 and S3 should be turned on.

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Figure 4.

DCMLI circuit topologies: (a) three-level; (b) five-level.

Figure 4b shows a five-level diode-clamped converter whose DC bus consists of four capacitors: C1, C2, C3, and C4. Here, the output voltage va has five levels: Vdc/2, Vdc/4, 0, Vdc/4, and Vdc/2. In this example, four complementary switches are (S1,S5), (S2,S6), (S3,S7), and (S4,S8). For voltage level Vdc/2, all upper switches S1 and S4 should be turned on; for voltage level Vdc/4, three upper switches S2 and S4 and one lower switch should be turned on; for voltage level 0, two upper switches S3 and S4 and two lower switches S5 and S6 should be turned on; for voltage level Vdc/4, one upper switch S4 and three lower switches S5 and S7 should be turned on; and for voltage level Vdc/2, all lower switches S5 and S8 should be turned on.

Development of DCMLI of a higher level is constrained by diodes rating for reverse voltage blocking. The number of diodes increases quadratic in the level of inverter; therefore, construction of DCMLI beyond certain level will be impractical. Moreover, the diode recovery time is the major challenge in high-voltage high-power applications [12].

4.1.2. Carrier-based PWM schemes for DCMLIs

For DCMLIs, two or more carrier waveforms are used to modulate the target waveform. The number of waveforms depends on the level of the converter. Usually, the level of an inverter is an odd number, and if L is the level of the converter, then the number of carrier waveforms is L1.

Carrier waveforms can be shifted with respect to each other. Based on the shift between the carrier waveforms, following modulation schemes are identified:

  • phase opposition disposition (POD): all carrier waveforms above zero are in phase and 180° out of phase with those below zero;

  • alternative phase opposition disposition (APOD): every carrier waveform is 180° out of phase with its neighbors;

  • phase disposition (PD): all carrier waveforms are in phase.

An example of each PWM scheme for a five-level inverter is shown in Figures 57. Apparently, there is no difference between POD and APOD for three-level inverters.

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Figure 5.

POD PWM scheme for a five-level inverter with the sinusoid reference waveform.

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Figure 6.

APOD PWM scheme for a five-level inverter with the sinusoid reference waveform.

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Figure 7.

PD PWM scheme for a five-level inverter with the sinusoid reference waveform.

4.1.3. Contour plots for DCMLIs

If L is the level of the inverter, it denotes N=(L1)/2. Then, function f(x,y) of voltage level assumes one of the values: NVdc/(L1), (N1)Vdc/(L1),,0,,NVdc/(L1). Let us denote carrier waveforms as x1c(t), x2c(t), …, xL1c(t) beginning from the lowest one. If the reference waveform is less than x1c(t), then f(x,y)=NVdc/(L1); if the reference waveform is greater than xi1c(t) and less than xic(t), i=2,,L1, then f(x,y)=(Ni+1)Vdc/(L1); and, finally, f(x,y)=NVdc/(L1) if the reference waveform is greater than xL1c(t).

To determine the corresponding contour plot, interval [π;π] of the y-axis should be divided in 2N1 intervals with limits defined by Mcosy=m/N, m=N,(N1),,N. One also needs to consider separately “rising” and “falling” edges of each carrier waveform corresponding to two intervals of variable x: πx0 and 0xπ. Then, the condition that the reference waveform is greater than the carrier waveform xic(t) for “rising” and “falling” edges becomes, respectively:

NMcosy>xicπ if 0xπ,
(9)
NMcosy>xicπ if πx0.
(10)

Similarly, the opposite conditions can be defined. Solving in Eqs. (9) and (10) for all values of f(x,y), one can find the contour plot of a particular PWM scheme, accounting for the voltage level in each domain. Examples of different PWM schemes for three- and five-level diode-clamped inverter are given in Figures 812.

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Figure 8.

PD PWM scheme for a three-level diode-clamped inverter.

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Figure 9.

POD PWM scheme for a three-level diode-clamped inverter.

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Figure 10.

PD PWM scheme for a five-level diode-clamped inverter (here ϕ2=πϕ1 and ϕ1=cos1(1/2M)).

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Figure 11.

POD PWM scheme for a five-level diode-clamped inverter (here ϕ2=πϕ1 and ϕ1=cos1(1/2M)).

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Figure 12.

APOD PWM scheme for a five-level diode-clamped inverter (here ϕ2=πϕ1 and ϕ1=cos1(1/2M)).

4.1.4. Harmonic spectra of DCMLIs

Once the unit cell with contour plots of voltage level domains for a particular PWM is obtained, harmonic components of the PWM can be found using Eq. (2) with the help of equations given in Section 2.2. Output voltage waveforms and their Fourier transforms are given below for three- and five-level diode-clamped inverters using different modulation strategies. Harmonic components magnitudes are plotted for first harmonic numbers assuming M=0.8 and ωc/ω0=40.

The output voltage of a three-level diode-clamped inverter modulated by NS POD/APOD PWM is given by

va(t)=VdcMcos(ω0t)+2Vdcπm=11mp=(1)pJ2p+1(mπM)cos(mωct+(2p+1)ω0t)
(11)

and its harmonic components are plotted in Figure 13.

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Figure 13.

Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using NS POD/APOD PWM.

The output voltage of a three-level diode-clamped inverter modulated using NS PD PWM can be calculated as

v(t)a=VdcMcos(ω0t)+2Vdcπq=112qp=J2p+1(2qπM)(1)p2s+1cos(2qωct+(2p+1)ω0t)++4Vdcπ2q=112q1p=s=J2s+1((2q1)πM)(1)p2p+2s+1cos((2q1)ωct+2pω0t)
(12)

and its theoretical harmonic spectrum is shown in Figure 14.

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Figure 14.

Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using NS PD PWM.

The output voltage of a five-level diode-clamped inverter obtained by NS POD PWM can be found as follows:

va(t)=2VdcMcos(ω0t)+2Vdcπq=112qp=(1)pJ2p+1(4qπM)cos(2qωct+(2p+1)ω0t)++4Vdcπ2q=112q1p=[(1)pJ2p+1(2(2q1)πM)(π22ϕ)+s=s+p+10(1)s+1J2s+1(2(2q1)πM)sin(2(p+s+1)ϕ)p+s+1],
(13)

where ϕ=cos1(1/2M) and its harmonic spectrum is plotted in Figure 15.

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Figure 15.

Theoretical harmonics spectrum of a five-level diode-clamped inverter modulated using NS POD PWM.

The output voltage of a five-level diode-clamped inverter modulated by NS APOD PWM is given by

va(t)=2VdcMcos(ω0t)+2Vdcπm=11mp=(1)m+pJ2p+1(2mπM)cos(mωct+(2p+1)ω0t)
(14)

and its harmonics are plotted in Figure 16.

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Figure 16.

Theoretical harmonic spectrum of a five-level diode-clamped inverter modulated using NS APOD PWM.

The output voltage of a five-level diode-clamped inverter modulated using NS PD PWM is given by

va(t)=2VdcMcos(ω0t)+2Vdcπq=112qp=(1)pJ2p+1(4qπM)cos(2qωct+(2p+1)ω0t)++4Vdcπ2q=112q1p=s=2p+2s1(1)sJ2s+1(2(2q1)πM)cos(π(p+s))sin(ϕ(2p+2s+1))2p+2s+1××cos((2q1)ωct+2pω0t)
(15)

where ϕ=cos1(1/2M) and the theoretical harmonics spectrum is shown in Figure 17.

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Figure 17.

Theoretical harmonic spectrum of a five-level diode-clamped inverter modulated using NS PD PWM.

Below theoretical harmonic contents for SR and AR PWM are presented for a three-level diode-clamped inverter. The output voltage of a three-level diode-clamped inverter modulated with SR POD PWM can be found using

Cm,2n+1=2Vdcqπ(1)nJ2n+1(qπM)
(16)

where q=m+nω0/ωc. Its harmonics content is shown in Figure 18.

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Figure 18.

Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using SR POD PWM.

The harmonic spectrum of a three-level diode-clamped inverter modulated with SR PD PWM can be determined by equations

Cm,2p=2Vdcπ21ejqπqk=(1)pJ2k+1(qπM)2p+2k+1
(17)
Cm,2p+1=Vdcπ1+ejqπq(1)pJ2p+1(qπM)
(18)

where q=m+nω0/ωc. First harmonics are plotted in Figure 19.

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Figure 19.

Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using SR PD PWM.

The harmonic spectrum of a three-level diode-clamped inverter modulated with AR POD PWM can be determined by equations

Cmn=2Vdc(1ejnπ)π2q[1nsin(nπω02ωc)sin(nπ2)+π2Jn(qπM)sin(nπ2[1ω0ωc])++k=n+k01n+kJk(qπM)sin(π2[knω0ωc])sin((n+k)π2)]
(19)

where q=m+nω0/ωc and n is odd. A series of lower order harmonics are shown in Figure 20.

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Figure 20.

Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using AR POD PWM.

The harmonic spectrum of a three-level diode-clamped inverter modulated with AR PD PWM can be found using equations

Cm0=2Vdcπ2qs=J2s+1(qπM)2s+1(1ej(q+2s)π)
(20)
Cmn=2Vdc(1+ejqπ)π2q[1nsin(nπ2ω0ωc)sin(nπ2)+(1)n+1π2Jn(qπM)sin(nπ2[1+ω0ωc])+k=kn(1)k+1n+kJk(qπM)sin([n+k]π2)sin(π2[k+nω0ωc])]
(21)

where q=m+nω0/ωc and n is odd in Eq. (21). A series of lower order harmonics are shown in Figure 21.

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Figure 21.

Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using AR PD PWM.

4.2. Cascaded H-Bridge MLI

4.2.1. CHBMLI circuit topology

A single-phase H-bridge inverter is shown in Figure 22. It is made up of two single-phase inverter legs (Figure 1) connected to a common DC bus. Each phase is modulated in complementary pattern by a carrier/reference waveform comparison when the switching occurs as it is described above. A single-phase full-bridge inverter generates voltage of three levels: Vdc, 0, and Vdc.

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Figure 22.

A single-phase H-bridge (full-bridge) inverter.

A cascaded H-bridge multilevel inverter, also called cascaded multicell inverters [12], consists of a number of series-connected single-phase H-bridge inverters connected to separate dc voltage sources. The resulting phase voltage is synthesized by addition of the voltages generated by different cells and is nearly sinusoidal even without filtering. An example of a five-level cascaded H-bridge inverter is shown in Figure 23.

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Figure 23.

A five-level cascaded H-bridge inverter topology.

Cascaded MLI topology has several advantages: each cell can be controlled independently from the others. Although communication between cells is required to achieve synchronized reference and carrier waveforms, controllers can be distributed. The control scheme is significantly easier than the ones for other topologies. However, it has not been used in practice in low power applications because a separate isolated dc voltage supply is needed for each full H-bridge [4].

4.2.2. Carrier-based PWM schemes for CBHMLIs

Three-level modulation of a single-phase full-bridge inverter can be obtained via combination of voltage modulations of two phase legs a and b. The phase legs are modulated with 180° opposed reference waveforms given by

vaid(t)=Vdc2Mcosy,
(22)
vbid(t)=Vdc2Mcos(yπ).
(23)

The fundamental line-to-line (l-l) output reference voltage for the inverter is the difference between two phase reference voltages and is equal to

vabid(t)=vaid(t)vbid(t)=VdcMcosy.
(24)

Then, the l-l output voltage harmonic components for the inverter are given by

vab(t)=va(t)vb(t).
(25)

Applying different PWM schemes to a single-phase half-bridge inverter, one can obtain various modulations for the full-bridge inverter: NS, SR, and AR.

4.2.3. Harmonic spectra of CHBMLIs

The harmonic solution for NS PWM of a phase leg is given by

va(t)=Vdc2+Vdc2Mcos(ω0t)+2Vdcπm=11mn=Jn(mπ2M)sin([m+n]π2)cos(mωct+nω0t).
(26)

Eq. (26) can be applied for each phase leg accounting for 180° phase shift of the reference waveforms resulting in the following harmonic spectrum for NS PWM of a full-bridge inverter:

vabNS(t)=VdcMcos(ω0t)+4Vdcπm=112mn=J2n+1(2mπM)cos([m+n]π)cos(2mωct+[2n+1]ω0t).
(27)

The harmonic spectrum of the output voltage of a full-bridge inverter modulated using SR PWM is equal to

vabSR(t)=4Vdcπ[n=1Jn(nω0ωcπ2M)nω0ωcsin(n[1+ω0ωc]π2)|sinnπ2|cos(nω0t)+m=1n=Jn([m+nω0ωc]π2M)m+nω0ωcsin([m+n+nω0ωc]π2)|sinnπ2|cos(mωct+nω0t)]
(28)

and using AR PWM it is given by

vabAR(t)=4Vdcπ[n=1Jn(nω0ωcπ2M)nω0ωcsin(nπ2)cos(nω0t)+m=1n=J2n1([m+nω0ωc]π2M)m+nω0ωcsin([m+n]π2)|sinnπ2|cos(mωct+nω0t)].
(29)

It can be seen that all odd carrier and associated sideband harmonics as well as even sideband harmonics are cancelled out from the l-l output voltage. A further cancellation can be obtained by appropriately phase shifting the remaining harmonics of several series-connected single-phase H-bridges. This process is called phase-shifted cascaded (PSC) PWM. The major principle is that the phase shift between two phases of each H-bridge cell is kept 180°, and then, carriers of each H-bridge are shifted with respect to each other. Optimum harmonic cancellation is achieved via phase shifting each carrier by (i1)π/N, where i is the ith converter, N is the number of series-connected single-phase inverter legs, and N=(L1)/2 and L is the number of voltage levels that can be achieved. This modulation is also called phase shift (PS) PWM. The overall cascaded inverter phase leg to dc link midpoint voltage can be obtained by adding up the l-l output reference voltages of each cell:

v(t)=i=1Nvabi(t).
(30)

One can see in Figures 2432 that carrier harmonics of odd order and even order sideband harmonics are cancelled out in the three-level CHB inverter for all presented topologies, and increasing the level of the inverter is leading to cancelling out other carrier harmonics of order mkN,k=1,2,3,...

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Figure 24.

Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using NS PS PWM.

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Figure 25.

Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using NS PS PWM.

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Figure 26.

Theoretical harmonic spectrum of a single-phase cascaded H-bridge inverter modulated using NS PS PWM.

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Figure 27.

Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using SR PS PWM.

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Figure 28.

Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using SR PS PWM.

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Figure 29.

Theoretical harmonic spectrum of a single-phase cascaded H-bridge inverter modulated using SR PS PWM.

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Figure 30.

Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using AR PS PWM.

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Figure 31.

Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using AR PS PWM.

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Figure 32.

Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using AR PS PWM.

5. Harmonic distortion

Modern power electronic equipment operates in different discrete modes which causes a deviation of the output waveform from the desirable sine waveform due to insertion of undesirable harmonics. The rate of the deviation is presented by a number of basic indices characterizing the harmonic distortion. In particular, these indices enable us to compare the effectiveness of various inverter modulation algorithms. The indices are introduced in this section, and different inverter topologies are compared in their terms.

5.1. Harmonic distortion indices

Given that the output voltage v(t) of a power converter is a periodic function with period T, the root-mean-square (RMS) value of the function is defined by

Vrms=1T0Tv(t)2dt.
(31)

Since v(t) is periodic with the Fourier series v(t)=V0+n=1Vncos(nωt+φn), the Parseval’s theorem can be used to find the RMS voltage of v(t):

Vrms=V02+n=1Vn22.
(32)

In most of the practical cases, the fundamental harmonic V1 can be considered as the desired output voltage. The reminder of this expression is then considered as a “distortion” to the output. Factoring out V1 gives us

Vrms=V1,rms1+2V02V12+n=2(VnV1)2,
(33)

where V1,rms=V1/2. The total harmonic distortion (THD) of the voltage is defined as

THD=2V02V12+n=2(VnV1)2
(34)

and the RMS voltage becomes

Vrms=V1,rms1+THD2.
(35)

For the purpose of comparing various switching strategies, the weighted total harmonic distortion (WTHD) is used:

WTHD=1V1n=2(Vnn)2
(36)

In the case of pulse-width-modulated inverters, the DC voltage remains constant, while the fundamental component varies. On the other hand, for the same ratio of switching to output frequency, the harmonic components vary relatively little, resulting in a large variation of THD and WTHD. Therefore, a normalized WTHD can be used. For the case of half-bridge inverter, the normalization factor is chosen to be the value of the fundamental ac voltage when the modulation index M equals 1, that is, Vdc. Thus, the normalized WTHD, WTHD0, becomes

WTHD0=n=21n2(VnVdc)2=WTHDV1Vdc=WTHDM.
(37)

5.2. Harmonic distortion indices for a DCMLI

Harmonic distortion indices for all presented inverter topologies and PWMs are provided in Table 1. Spectra are evaluated for M=0.8 and ωc/ω0=40. It can be noted that a half-bridge inverters and full-bridge inverters demonstrate similar waveform quality regardless the PWM strategy applied. Cascaded H-bridge inverters show improvement in performance with increase in number of levels, which appears due to extensive harmonics cancelations up to harmonics of a high order. Performance of diode-clamped inverters also improves with increasing number of levels; however, the improvement is significantly lower than for the cascaded H-bridge inverters.

Vrms (p.u.)THD (%)WTHD (%)WTHD0 (%)
Three-level diode-clamped inverter phase leg
NS POD/APOD PWM0.695971.661.581.27
NS PD PWM0.695971.651.581.27
SR POD/APOD PWM0.695971.761.591.27
SR PD PWM0.700373.233.702.96
AR POD/APOD PWM0.695671.611.581.26
AR PD PWM0.613142.371.821.46
Five-level diode-clamped inverter phase leg
NS POD PWM0.679065.911.571.26
NS PD PWM0.645755.021.301.04
NS APOD PWM0.600735.710.810.65
Five-level cascaded H-bridge inverter phase leg
AR PS PWM0.592931.440.200.16
SR PS PWM0.663861.600.670.53
NS PS PWM0.593031.430.200.16
Three-level cascaded H-bridge inverter phase leg
AR PS PWM0.685668.500.790.63
SR PS PWM0.685668.670.790.64
NS PS PWM0.685668.470.790.63
Single phase half-bridge inverter
AR PWM0.4796136.982.872.30
SR PWM0.4797137.152.872.30
NS PWM0.4796136.932.872.30

Table 1.

Harmonic distortion factors for MLI.

There is a substantial difference between different modulations used for the same converter. For example, AR PD is showing the worst performance among all other carrier-based modulations of a three-level DC inverter which can be explained by the fact that very few harmonics are cancelled unlike the other modulations.

6. Conclusion

In this chapter, an application of double Fourier series to analytical analysis of power width modulation of power electronic converters was presented. The pulse width modulation concept was given, and different pulse width modulation schemes were described. Harmonic spectra and various distortion factors were calculated for various inverter topologies, namely three- and five-level diode-clamped inverters, three- and five-level cascaded H-bridge inverters, and modulated using different PWM schemes. PWM schemes performance varied for different converter topologies; therefore, the preferable PWM strategy is usually determined by a specific converter topology.

Comparing different topologies, the cascaded H-bridge topology contains the least number of sideband harmonics, and they can be further eliminated by increasing the number of levels of the inverter. DCMLIs and CCMLIs are constrained in the number of levels due to diodes physical properties.

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