Harmonic distortion factors for MLI.
Many power electronic applications demand generation of voltage of a rather good sinusoidal waveform. In particular, dc-to-ac voltage conversion could be done by multilevel inverters (MLI). A number of various inverter topologies have been suggested so far: diode-clamped (DC) MLI, capacitor-clamped (CC) MLI, cascaded H-bridge (CHB) MLI, and others. Fourier series expansions have been used to investigate and to form a basis of different topologies comparison, to discover their advantages and disadvantages, and to determine their control. In this chapter, we discuss modulation strategies of DCMLI and CHBMLI, solve their harmonics spectra analytically, and compare them using harmonic distortion indices.
- Fourier series
- multilevel inverters
- pulse width modulation
The term “power electronics” is used for a family of electrical circuits which convert electrical energy from one level of voltage/current/frequency to other using semiconductor-based switches. The switching process in power electronic converters is called modulation, and development of optimum modulation strategies has been the subject of research in power engineering during several past decades. Electrical power conversion has evolved as new topologies, switching devices, control, and modulation strategies have been proposed. Each group of power electronic converters has its own preferable modulation approach optimizing the circuit performance, addressing such issues as switching frequency, distortion, losses, and harmonics generation. Only voltage source inverters modulation will be discussed below.
Before turning to specific issues of modulation, one needs to establish a common basis to compare the modulation schemes. Different merits are used to evaluate a particular pulse width modulation (PWM) implementation: diminished harmonics , filtered distortion performance factors , and the root-mean-square (RMS) harmonic ripple current . In this text, analytical solutions to PWM strategies are used to compare magnitude of various harmonic components. This approach has a number of advantages .
Firstly, the conventional method of determining harmonic components of a switched waveform using fast Fourier transform (FFT) of the waveform is sensitive to the time resolution of the simulation and periodicity of the overall waveform. Moreover, it ensures that intrinsic harmonic components of PWMs are not affected by such factors as simulation round off errors, dead time, switch ON-state voltages, DC bus ripple voltages, etc.
Secondly, PWM strategies can be compared at exactly the same phase leg switching frequency.
And thirdly, the first-order weighted total harmonic distortion (WTHD) is used for a quick comparison of PWMs since it has a physical meaning (the normalized current ripple expected into an inductive load when fed from the switched waveform) and often used performance indicator.
The rest of the paper is organized as follows. In Section 2, information on the double Fourier series expansions and necessary relations is given. Essentials on PWM are provided in Section 3. Different voltage inverter topologies and their analytical PWM solutions are presented in Section 4. Harmonic distortion factors of the introduced inverter topologies, different modulation schemes are compared in Section 5, and a summary on the chapter is given in Section 6.
2. Double Fourier series expansion
2.1. Double Fourier series decomposition for a double variable function
It is well known that a periodic two variable waveform can be expressed in the form
where the double Fourier series components can be found in a complex form:
The first term in Eq. (1) is the DC offset that should be zero or negligibly small. The second summation term represents the baseband harmonics. The first baseband harmonic, , is the fundamental harmonic whose magnitude defines the magnitude of the output waveform. Other baseband harmonics, , represent low-frequency undesired fluctuations about the fundamental output and should preferably be eliminated with the modulation process. The third summation term in Eq. (1) corresponds to the carrier harmonics which are relatively high-frequency components. Finally, the last double summation term in Eq. (1) corresponds to groups of the sideband harmonics of order n located around the mth carrier harmonic component.
2.2. Jacobi-Anger expansion and Bessel functions relations
The magnitudes of harmonic components in Eq. (1) are to be determined for each PWM scheme for each particular combination of indexes and . The evaluations are based on Jacobi-Anger expansions
and a number of Bessel function properties: and , that particularly implies .
2.3. Parseval’s theorem
Givenis a periodic function with the period , it can be represented by its Fourier series where is the fundamental angular frequency. Then, on , the Parseval’s theorem assumes the form
3. Pulse width modulation
To introduce the concept of PWM, let us consider a basic configuration of one-phase two-level inverter leg shown in Figure 1. It consists of two switches, and , and two diodes, and . Switches and are operating alternately at high frequency to generate a quasiperiodic output voltage , whose low-frequency components are intended to deliver a prescribed AC supply. When the switch () is ON, a positive voltage, , (respectively, negative voltage, ) is supplied to a load at the connection point .
The essential concept of a two-level pulse-width-modulated converter system is that a low-frequency target waveform is compared against a high-frequency carrier waveform, and the comparison result is used to control the state of a switched phase leg. In case of the inverter in Figure 1, the phase leg is switched to the upper DC rail when the target waveform is greater than the carrier waveform, otherwise to the lower DC rail. As a result, a sequence of pulses switching between the upper and the lower DC rails is generated, which contains the target waveform as the fundamental component but also a series of unwanted harmonics arising due to the switching process.
The most well-known analytical method of determining the harmonic components of a PWM switched phase leg was first developed by Bowes and Bullough , who adopted an analysis approach originally developed for communication systems by Bennet  and Black  to modulated converter systems.
The analysis is based on the existence of two time variables and , where and are the angular frequencies of the fundamental (target, sinusoid) low-frequency modulated waveform and the carrier high-frequency modulating waveform, .Variables and are considered to be independently periodic. If the ratio is integer, the generated pulse width trail will be periodic .
The problem of finding a PWM for the modulated periodic waveform can be solved by exploring a unit cell which identifies contours within which remains constant for cyclic variations of and and is equal to the phase leg output voltage. Thus, a three-dimensional (3D) unit cell is a plot of two time variables function with assuming values of where and vary from to . Contours of within the unit cell depend on a particular PWM strategy which will be discussed below.
3.1. Carrier-based PWM schemes
3.1.1. Carrier waveforms and unit cells
Since the target waveform is usually a sinusoid, PWM schemes can be categorized based on the carrier waveform: saw-tooth leading edge (Figure 2a), saw-tooth trailing edge (Figure 2b), and double edge (Figure 2c).
Let the modulated waveform of a phase be given , where is the modulation index, . For the one-phase two-level inverter leg shown in Figure 1, unit cells with contour plots for each carrier waveform modulation are presented in Figure 3. The output of the modulated waveform assumes either or , and the regions of the constant output are bounded by reference waveforms . For saw-tooth modulations, one of switching time instances (within a period of the carrier waveform) is independent of the reference waveform resulting in only one side of the contour plot to be sinusoid. The double-edge PWM both sides of the switched output are modulated providing better harmonic performance unlike saw-tooth modulations . Hereinafter, only double-edge modulation is considered.
To determine the harmonics content and the output waveform of a particular PWM, the double Fourier series coefficients (or, equivalently, and ) are to be found using Eq. (2). To solve the problem, the periodic function is to be integrated over the unit cell of the PWM scheme.
3.1.2. PWM sampling schemes
Based on the choice of switching time instances, PWM schemes can be divided into: naturally sampled (NS), symmetrically regularly sampled (SR), and asymmetrically regularly sampled (AR) PWMs.
18.104.22.168. Naturally sampled PWM
For NS PWM scheme, switching occurs at time instances corresponding to intersection of the carrier and target waveforms. Switching time instances can also be determined as the intersection between the reference waveform and the solution trajectory . For example, switching time instances for the NS double-edge modulation of the one-phase two-level inverter leg in Figure 1 are defined from its unit cell in Figure 3c such that changes
from to when ,
from to when .
22.214.171.124. Symmetrically regularly sampled PWM
Switching instances for SR PWM can be determined by the intersection between the sampled sinusoid waveform and the solution trajectory line . The same switching instances can be determined as the intersection between the continuous sinusoid waveform and a staircase variable which has a constant value within each carrier interval . In general, the value of within each carrier interval can be expressed as
where represents the pth carrier interval within a fundamental cycle. The staircase variable in terms of continuous variables and is given by
The double Fourier series coefficients for the case of SR PWM with a triangle carrier can be found analogously to NS PWM with variable substituted by variable found from Eq. (6).
Considering the previous example with the one-phase two-level inverter leg shown in Figure 1, switching time instances for the SR double-edge modulation are defined such that changes
from to when ,
from to when .
126.96.36.199. Asymmetrically regularly sampled PWM
Switching time instances for AR PWM are determined similarly to SR PWM. Unlike SR PWM, switching occurs twice within each carrier interval for AR PWM. The switching time instances can be determined as the intersection between the continuous sinusoid waveform and two staircase variables
which can be expressed in terms of continuous variables and as
To write the double Fourier series integral for AR PWM, the switched waveform in each carrier interval must be split into two sections for analysis, and with the results added by superposition, the first section () has modulated “rising” edge in the first half carrier interval and a “falling” edge in the center of the carrier interval. The second section () has a modulated “rising” edge in the center of the carrier interval and “falling” edge in the second half carrier interval. Mathematically, this behavior can be expressed as a sum of two functions, and , representing “rising” and “falling” edges of the double-edge carrier waveform .
In the previous example with the one-phase two-level inverter leg (Figure 1), functions and are defined as follows:
steps from to at and from to at ;
steps from to at and from to at .
4. PWM for multilevel inverters
In this section, the following MLI topologies are presented: diode-clamped (DC) MLI, cascade H-bridge (CHB) MLI, and capacitor-clamped (CC) MLI. The three-level diode-clamped inverter, which is also called the neutral-point-clamped inverter, was initially introduced by Nabae et al.  in 1981. Thereafter, diode-clamped, cascade H-bridge, and flying capacitor MLIs with higher number of DC voltage levels have been developed [9–11].
4.1. Diode-clamped MLI
4.1.1. DCMLI circuit topology
A three-level diode-clamped inverter is shown in Figure 4a. In this circuit, the DC bus voltage is split into three levels by two series-connected bulk capacitors, and . The middle point of the two capacitors can be defined as a neutral point. The inverter has two complementary switch pairs: and ; the complementary switches cannot be turned on simultaneously. The output voltage has three states: , , and . For voltage level , switches and should be turned on; for , switches and should be turned on; and for the level, switches and should be turned on.
Figure 4b shows a five-level diode-clamped converter whose DC bus consists of four capacitors: , , , and . Here, the output voltage has five levels: , , , , and . In this example, four complementary switches are , , , and . For voltage level , all upper switches and should be turned on; for voltage level , three upper switches and and one lower switch should be turned on; for voltage level , two upper switches and and two lower switches and should be turned on; for voltage level , one upper switch and three lower switches and should be turned on; and for voltage level , all lower switches and should be turned on.
Development of DCMLI of a higher level is constrained by diodes rating for reverse voltage blocking. The number of diodes increases quadratic in the level of inverter; therefore, construction of DCMLI beyond certain level will be impractical. Moreover, the diode recovery time is the major challenge in high-voltage high-power applications .
4.1.2. Carrier-based PWM schemes for DCMLIs
For DCMLIs, two or more carrier waveforms are used to modulate the target waveform. The number of waveforms depends on the level of the converter. Usually, the level of an inverter is an odd number, and if is the level of the converter, then the number of carrier waveforms is .
Carrier waveforms can be shifted with respect to each other. Based on the shift between the carrier waveforms, following modulation schemes are identified:
phase opposition disposition (POD): all carrier waveforms above zero are in phase and out of phase with those below zero;
alternative phase opposition disposition (APOD): every carrier waveform is out of phase with its neighbors;
phase disposition (PD): all carrier waveforms are in phase.
4.1.3. Contour plots for DCMLIs
If is the level of the inverter, it denotes . Then, function of voltage level assumes one of the values: , . Let us denote carrier waveforms as , , …, beginning from the lowest one. If the reference waveform is less than , then ; if the reference waveform is greater than and less than , , then ; and, finally, if the reference waveform is greater than .
To determine the corresponding contour plot, interval of the y-axis should be divided in intervals with limits defined by , . One also needs to consider separately “rising” and “falling” edges of each carrier waveform corresponding to two intervals of variable : and . Then, the condition that the reference waveform is greater than the carrier waveform for “rising” and “falling” edges becomes, respectively:
Similarly, the opposite conditions can be defined. Solving in Eqs. (9) and (10) for all values of , one can find the contour plot of a particular PWM scheme, accounting for the voltage level in each domain. Examples of different PWM schemes for three- and five-level diode-clamped inverter are given in Figures 8–12.
4.1.4. Harmonic spectra of DCMLIs
Once the unit cell with contour plots of voltage level domains for a particular PWM is obtained, harmonic components of the PWM can be found using Eq. (2) with the help of equations given in Section 2.2. Output voltage waveforms and their Fourier transforms are given below for three- and five-level diode-clamped inverters using different modulation strategies. Harmonic components magnitudes are plotted for first harmonic numbers assuming and .
The output voltage of a three-level diode-clamped inverter modulated by NS POD/APOD PWM is given by
and its harmonic components are plotted in Figure 13.
The output voltage of a three-level diode-clamped inverter modulated using NS PD PWM can be calculated as
and its theoretical harmonic spectrum is shown in Figure 14.
The output voltage of a five-level diode-clamped inverter obtained by NS POD PWM can be found as follows:
where and its harmonic spectrum is plotted in Figure 15.
The output voltage of a five-level diode-clamped inverter modulated by NS APOD PWM is given by
and its harmonics are plotted in Figure 16.
The output voltage of a five-level diode-clamped inverter modulated using NS PD PWM is given by
where and the theoretical harmonics spectrum is shown in Figure 17.
Below theoretical harmonic contents for SR and AR PWM are presented for a three-level diode-clamped inverter. The output voltage of a three-level diode-clamped inverter modulated with SR POD PWM can be found using
where . Its harmonics content is shown in Figure 18.
The harmonic spectrum of a three-level diode-clamped inverter modulated with SR PD PWM can be determined by equations
where . First harmonics are plotted in Figure 19.
The harmonic spectrum of a three-level diode-clamped inverter modulated with AR POD PWM can be determined by equations
where and is odd. A series of lower order harmonics are shown in Figure 20.
The harmonic spectrum of a three-level diode-clamped inverter modulated with AR PD PWM can be found using equations
4.2. Cascaded H-Bridge MLI
4.2.1. CHBMLI circuit topology
A single-phase H-bridge inverter is shown in Figure 22. It is made up of two single-phase inverter legs (Figure 1) connected to a common DC bus. Each phase is modulated in complementary pattern by a carrier/reference waveform comparison when the switching occurs as it is described above. A single-phase full-bridge inverter generates voltage of three levels: , 0, and
A cascaded H-bridge multilevel inverter, also called cascaded multicell inverters , consists of a number of series-connected single-phase H-bridge inverters connected to separate dc voltage sources. The resulting phase voltage is synthesized by addition of the voltages generated by different cells and is nearly sinusoidal even without filtering. An example of a five-level cascaded H-bridge inverter is shown in Figure 23.
Cascaded MLI topology has several advantages: each cell can be controlled independently from the others. Although communication between cells is required to achieve synchronized reference and carrier waveforms, controllers can be distributed. The control scheme is significantly easier than the ones for other topologies. However, it has not been used in practice in low power applications because a separate isolated dc voltage supply is needed for each full H-bridge .
4.2.2. Carrier-based PWM schemes for CBHMLIs
Three-level modulation of a single-phase full-bridge inverter can be obtained via combination of voltage modulations of two phase legs and . The phase legs are modulated with opposed reference waveforms given by
The fundamental line-to-line (l-l) output reference voltage for the inverter is the difference between two phase reference voltages and is equal to
Then, the l-l output voltage harmonic components for the inverter are given by
Applying different PWM schemes to a single-phase half-bridge inverter, one can obtain various modulations for the full-bridge inverter: NS, SR, and AR.
4.2.3. Harmonic spectra of CHBMLIs
The harmonic solution for NS PWM of a phase leg is given by
Eq. (26) can be applied for each phase leg accounting for phase shift of the reference waveforms resulting in the following harmonic spectrum for NS PWM of a full-bridge inverter:
The harmonic spectrum of the output voltage of a full-bridge inverter modulated using SR PWM is equal to
and using AR PWM it is given by
It can be seen that all odd carrier and associated sideband harmonics as well as even sideband harmonics are cancelled out from the l-l output voltage. A further cancellation can be obtained by appropriately phase shifting the remaining harmonics of several series-connected single-phase H-bridges. This process is called phase-shifted cascaded (PSC) PWM. The major principle is that the phase shift between two phases of each H-bridge cell is kept , and then, carriers of each H-bridge are shifted with respect to each other. Optimum harmonic cancellation is achieved via phase shifting each carrier by , where is the ith converter, is the number of series-connected single-phase inverter legs, and and is the number of voltage levels that can be achieved. This modulation is also called phase shift (PS) PWM. The overall cascaded inverter phase leg to dc link midpoint voltage can be obtained by adding up the l-l output reference voltages of each cell:
One can see in Figures 24–32 that carrier harmonics of odd order and even order sideband harmonics are cancelled out in the three-level CHB inverter for all presented topologies, and increasing the level of the inverter is leading to cancelling out other carrier harmonics of order
5. Harmonic distortion
Modern power electronic equipment operates in different discrete modes which causes a deviation of the output waveform from the desirable sine waveform due to insertion of undesirable harmonics. The rate of the deviation is presented by a number of basic indices characterizing the harmonic distortion. In particular, these indices enable us to compare the effectiveness of various inverter modulation algorithms. The indices are introduced in this section, and different inverter topologies are compared in their terms.
5.1. Harmonic distortion indices
Given that the output voltage of a power converter is a periodic function with period , the root-mean-square (RMS) value of the function is defined by
Since is periodic with the Fourier series , the Parseval’s theorem can be used to find the RMS voltage of :
In most of the practical cases, the fundamental harmonic can be considered as the desired output voltage. The reminder of this expression is then considered as a “distortion” to the output. Factoring out gives us
where . The total harmonic distortion (THD) of the voltage is defined as
and the RMS voltage becomes
For the purpose of comparing various switching strategies, the weighted total harmonic distortion (WTHD) is used:
In the case of pulse-width-modulated inverters, the DC voltage remains constant, while the fundamental component varies. On the other hand, for the same ratio of switching to output frequency, the harmonic components vary relatively little, resulting in a large variation of THD and WTHD. Therefore, a normalized WTHD can be used. For the case of half-bridge inverter, the normalization factor is chosen to be the value of the fundamental ac voltage when the modulation index equals 1, that is, . Thus, the normalized WTHD, WTHD0, becomes
5.2. Harmonic distortion indices for a DCMLI
Harmonic distortion indices for all presented inverter topologies and PWMs are provided in Table 1. Spectra are evaluated for and . It can be noted that a half-bridge inverters and full-bridge inverters demonstrate similar waveform quality regardless the PWM strategy applied. Cascaded H-bridge inverters show improvement in performance with increase in number of levels, which appears due to extensive harmonics cancelations up to harmonics of a high order. Performance of diode-clamped inverters also improves with increasing number of levels; however, the improvement is significantly lower than for the cascaded H-bridge inverters.
|(p.u.)||THD (%)||WTHD (%)||WTHD0 (%)|
|Three-level diode-clamped inverter phase leg|
|NS POD/APOD PWM||0.6959||71.66||1.58||1.27|
|NS PD PWM||0.6959||71.65||1.58||1.27|
|SR POD/APOD PWM||0.6959||71.76||1.59||1.27|
|SR PD PWM||0.7003||73.23||3.70||2.96|
|AR POD/APOD PWM||0.6956||71.61||1.58||1.26|
|AR PD PWM||0.6131||42.37||1.82||1.46|
|Five-level diode-clamped inverter phase leg|
|NS POD PWM||0.6790||65.91||1.57||1.26|
|NS PD PWM||0.6457||55.02||1.30||1.04|
|NS APOD PWM||0.6007||35.71||0.81||0.65|
|Five-level cascaded H-bridge inverter phase leg|
|AR PS PWM||0.5929||31.44||0.20||0.16|
|SR PS PWM||0.6638||61.60||0.67||0.53|
|NS PS PWM||0.5930||31.43||0.20||0.16|
|Three-level cascaded H-bridge inverter phase leg|
|AR PS PWM||0.6856||68.50||0.79||0.63|
|SR PS PWM||0.6856||68.67||0.79||0.64|
|NS PS PWM||0.6856||68.47||0.79||0.63|
|Single phase half-bridge inverter|
There is a substantial difference between different modulations used for the same converter. For example, AR PD is showing the worst performance among all other carrier-based modulations of a three-level DC inverter which can be explained by the fact that very few harmonics are cancelled unlike the other modulations.
In this chapter, an application of double Fourier series to analytical analysis of power width modulation of power electronic converters was presented. The pulse width modulation concept was given, and different pulse width modulation schemes were described. Harmonic spectra and various distortion factors were calculated for various inverter topologies, namely three- and five-level diode-clamped inverters, three- and five-level cascaded H-bridge inverters, and modulated using different PWM schemes. PWM schemes performance varied for different converter topologies; therefore, the preferable PWM strategy is usually determined by a specific converter topology.
Comparing different topologies, the cascaded H-bridge topology contains the least number of sideband harmonics, and they can be further eliminated by increasing the number of levels of the inverter. DCMLIs and CCMLIs are constrained in the number of levels due to diodes physical properties.