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A VLSI Architecture for Output Probability and Likelihood Score Computations of HMM-Based Recognition Systems

By Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi and Naofumi Takagi

Submitted: June 15th 2011Reviewed: November 8th 2011Published: March 16th 2012

DOI: 10.5772/38223

Downloaded: 1636

© 2012 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution 3.0 License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Kazuhiro Nakamura, Ryo Shimazaki, Masatoshi Yamamoto, Kazuyoshi Takagi and Naofumi Takagi (March 16th 2012). A VLSI Architecture for Output Probability and Likelihood Score Computations of HMM-Based Recognition Systems, Embedded Systems Kiyofumi Tanaka, IntechOpen, DOI: 10.5772/38223. Available from:

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