Conduction parameters extracted using several methods for Si(100) p-MOSFETs at Vd = 50 mV .
Authors investigate the carrier mobility in field-effect transistors mainly when fabricated on Si(110) wafers. They showed that the methods developed to extract the conduction parameters cannot be implemented for Si(110) p-MOSFETs. Authors then developed a more accurate mobility model able to simulate not only the drivability but also the transconductance for these same devices. The study of the relation between the mobility, channel direction and wafer orientation revealed that the channel direction had a significant impact on the mobility for transistors fabricated on Si(110) wafers, the highest electron and hole mobilites being obtained for a channel along the <100> and <110> directions, respectively. No relations were found for Si(100) wafers. The study of the dependence of the scattering mechanism limiting the mobility in Si(110) n-MOSFETs showed that the Coulomb and surface roughness scattering mechanisms were responsible for the degradation of the mobility when compared to the one on Si(100) wafers. Finally, the measurement of the mobility in an accumulation-mode MOSFETs is not straightforward since a bulk contribution, owing to the SOI layer, is adding to channel current. A methodology has been successfully implemented that led to the experimental verification of the universal behaviour of the mobility in an accumulation layer.
- crystallographic orientation
- channel direction
- scattering mechanism
The concept of employing an electric field to modulate the conductivity of a channel has been proposed first by Lilienfeld during the 1930s , long before its practical fabrication by Shockley et al. in 1947 . Since, the field-effect transistor has taken several directions and is at the root of various devices such as the metal-oxide-semiconductor FET (MOSFET) , dual gate MOSFET , junction FET , high electron mobility transistor , four-gate transistor  and so on. Nevertheless, the most important parameter for all these devices is the mobility of the carrier flowing inside the channel. Their mobility, also known as their ability to move through the crystal, will define the electrical performances of the device. The mobility is consequently a paramount parameter, and its good knowledge is of prime importance to first understand the physics underlying the conduction mechanisms inside semiconductor devices and second to be able to model and simulate a single transistor and in turn more complex circuits. The mobility in field-effect transistors hinges on various physical and environmental parameters that we propose to investigate for MOSFETs fabricated on (100) and (110) silicon-oriented wafers.
In Section 2, the method to measure the mobility is briefly reviewed for different structures, while Section 3 investigates several methods to extract the conduction parameters such as the low field mobility in Si(100) and Si(110) p-MOSFETs. Thus, its modeling is presented in Section 4 for the same devices. Results regarding the impact of the channel direction and wafer orientation on the mobility are investigated in Section 5 while the impact of the temperature is reported in Section 6 for Si(110) n-MOSFETs. Recently, devices based on the majority carriers rather than the minority ones to generate the current showed promising results. A methodology to extract their mobility is presented in Section 7 and is applied to accumulation-mode Si(100) p-MOSFETs. Finally, Section 8 concludes the chapter.
2. Experimental measurement of the mobility
The knowledge of the experimental mobility of carriers that are flowing inside the channel of a FET is essential for the development of semiconductor devices and in turn electronic circuits. The direct measurement of the effective mobility μeff is not possible, but its calculation is enabled through the measurement of the drain current Id—gate voltage Vg characteristic and of the gate-channel capacitance C as a function of the gate voltage. Both characteristics can be measured at Vd = 100 mV on a large gate transistor with at least a gate length L and gate width W above 50 μm in order to allow an accurate measurement of the capacitance. The substrate, source and drain electrodes are grounded, and the measurement of the capacitance is carried out on the gate electrode side at relatively low frequencies f between 1 and 100 kHz to neglect the serie resistances. Thus, the inversion charge Qinv per unit area is calculated from the C – Vg characteristic
The effective mobility μeff is finally calculated from
At this stage, the effective mobility can be plotted as a function of the carrier sheet density by dividing the inversion charge Qinv by the elementary charge q. It can also be plotted as a function of the transverse effective electric field Eeff that is calculated as follows:
where Qdep is the depletion charge per unit area, εSi is the dielectric constant of the silicon, ε0 is the permittivity of the vacuum, and η is a term referring to the averaging of the transverse electric field over the carrier distribution inside the conduction channel. In Eq. (3), the depletion charge Qdep is theoretically calculated from the doping concentration Nsub of the channel. It is expressed as follows:
being the bulk Fermi energy. In Eq. (5), kB is the Boltzmann constant, T is the temperature in Kelvin, and ni is the intrinsic carrier concentration. Takagi et al.  confirmed experimentally that in Eq. (3), η is equal to 1/3 for hole and to 1/2 for electron on Si(100) wafers . Regarding Si(110) wafers, η is generally taken equal to 1/3 for both hole [3, 10] and electron .
Contrary to bulk transistors for which the methodology has been described previously, the substrate of transistors fabricated on silicon-on-insulator (SOI) wafers sometimes cannot be accessed and then cannot be grounded. The back-gate cannot be biased and can be floating as long as the applied gate voltage is large enough to neglect the impact of the back-gate . The expression of the depletion charge Qdep given by Eq. (4) must be rearranged in Eq. (3) since the buried oxide is preventing the expansion of the depletion. If the depletion is expending deeper than the buried oxide, Qdep is given by qNsubtSOI where tSOI is the thickness of the SOI layer.
In the case of devices involving the majority carriers rather than the minority ones such as accumulation-mode transistors that will be studied in Section 7, the entire SOI layer is neutral when the accumulation layer is formed. The depletion charge Qdep in Eq. (3) must be removed, and the calculation is involving the sole accumulation charge Qacc [13, 14]. Eqs. (3) and (4) are rewritten as follows:
3. Mobility extraction methods
The knowledge of the conduction parameters is useful to model the drivability of a MOSFET and in turn simulate complex circuits. All extraction methods rely on the knowledge of the Id – Vg drain current-gate voltage characteristic measured for various gate lengths L and gate widths W.
The calculation procedures are based on the expression of the drain current in the linear region for a gate overdrive voltage Vg−Vth (Vth being the threshold voltage) greater than the drain voltage Vd (Vg−Vth>>Vd). In this range, the drain current Id is expressed as follows:
where Racc is the parasitic access resistances located at the source and drain contacts and Cox is the oxide capacitance. ΔW and ΔL are, respectively, the width and length gate channel reduction. In Eq. (8), the effective mobility μeff is generally replaced by the well known :
where μ0 is the low field mobility and θ is the mobility attenuation factor.
Depending on the extraction method, it is possible to obtain the low field mobility μ0, the mobility attenuation factor θ, the parasitic access resistance Racc in series with the intrinsic resistance of the channel of the transistor, the channel width reduction ΔW and the channel length reduction ΔL.
3.1. Silicon wafers with a (100) crystallographic orientation
Four different extraction methods have been used to extract the conduction parameters in p-MOSFETs fabricated on (100) silicon-oriented wafers. These methods are the Schreutelkamp method [16, 17], the interpolation method explained in Tsividis book , the Ghibaudo method  and finally the Ciofi method .
The Schreutelkamp method is based on Eqs. (8) and (9) and requires the calculation of intermediate parameters around a given gate overdrive voltage Vg−Vth that has been measured on several transistors featuring various gate length L for a given gate width W. A representation of this method is shown in Figure 1 for Vg−Vth = 1 V. Id−1 is plotted as a function of the gate length L, and the intersection with the vertical and horizontal axis is collected as shown in the inset of Figure 1. The low field mobility μ0 is extracted from the slope of the linear plot (1/Id)int/Lint versus (Vg – Vth)−1, while the mobility attenuation factor θ is obtained from the intersection with the vertical axis. On the other hand, the intersection of the plot Lint versus Lint/(1/Id)int with the vertical axis gives the channel length reduction ΔL, and the intersection with the horizontal axis gives the parasitic access resistance Racc. The extracted data according to the Schreutelkamp method on Si(100) p-MOSFETs are reported in Table 1. Note that the Schreutelkamp method does not allow the obtaining of the gate width reduction ΔW. The impact of the centered gate overdrive voltage Vg – Vth on the conduction parameters has been conducted. The results on the low field mobility μ0 and channel length reduction ΔL are shown in Figure 2. Both values are strongly decreasing when the gate overdrive voltage is increased until Vg – Vth = 0.8 V and are reaching a more stable behavior afterwards. For Vg – Vth < 0.8 V, the transistor is not working in the linear regime, and Eq. (8) is inaccurate, thus the fast drop. Additionally, the mobility model does not fit accurately the effective mobility, making the calculation even more inaccurate. For Vg – Vth > 0.8 V, the low field mobility μ0 is slightly increasing, while the channel length reduction ΔL is slightly decreasing. The reason is that even if Eq. (8) can be applied, Eq. (9) does not perfectly model the effective mobility. For each centered Vg – Vth, the parameters that are modeling the mobility are slightly changing in order to accurately fit the effective mobility according to the centered Vg – Vth. In turns, the channel length reduction ΔL and the low field mobility μ0 are not constant. An equivalent behavior has been also acknowledged when the mobility attenuation factor θ and the parasitic access resistance Racc have been plotted as a function of the centered gate overdrive voltage Vg – Vth.
Like the previous method, the one developed by Ghibaudo is also based on the same equations; however, the calculation requires the derivative of the Id – Vg curves for different gate length L and gate width W, that is the transconductance gm. Data measured around the threshold voltage are used. The plots Id/gm0.5 and gm−0.5 as a function of Vg – Vth allow the extraction of the intermediate parameters Gm and θ*, respectively, since Id/gm0.5 = (GmVd)0.5(Vg – Vth) and gm−0.5=(GmVd)−0.5[1 + θ*(Vg – Vth)]. Note that, the linear fittings are realized in the range Vg>Vth. The slope of the former fitting gives Gm, while the latter one allows the extraction of θ*. Thus, the intersection of the plot Gm versus W with the horizontal axis gives the gate width reduction ΔW, and the intersection of the plot Gm−1 versus L gives the gate length reduction ΔL. Finally, the mobility attenuation factor θ and the parasitic access resistances Racc are obtained from the plot θ* versus Gm since θ*=θ + GmRacc. θ* is the extrinsic mobility attenuation factor. The extracted parameters for Si(100) p-MOSFETs using the Ghibaudo method are reported in Table 1.
While the Ghibaudo method is making use of the derivative, the extraction method developed by Ciofi is based on the numerical analysis of the discretization of the Id – Vg characteristics and requires here as well the calculation of two intermediate parameters, K and H. They are extracted from the plot Vd/Id versus Vg – Vth for several gate lengths L and gate widths W since Vd/Id=K−1((Vg – Vth)−1 + H). H and K are related together by H=θ + KRacc, and the plot H versus K allows the obtaining of the mobility attenuation factor θ and the parasitic access resistances Racc. Plotting K−1 versus L and K versus W, respectively, gives the gate length reduction ΔL and the gate width reduction ΔW at the intersection with the horizontal axis. Data measured at relatively high gate overdrive voltage for Si(100) p-MOSFETs have been used, and the results of the Ciofi method are reported in Table 1. θ* versus Gm for the Ghibaudo method and H versus K for the Ciofi method have been plotted on the same Figure 3. The results in Figure 3 are almost identical for both methods, so are the units. In fact, K and Gm are the transconductance parameter and equals to μ0CoxW/L. Moreover, the similarity between both methods is obvious since θ + KRacc=H=θ*=θ + GmRacc. Note that, for both the Ghibaudo and the Ciofi methods, the knowledge of the threshold voltage Vth prior their implementation is not mandatory since the threshold voltage Vth can be extracted during the procedures described above.
Even if the method is quite limited since the low field mobility μ0 and the mobility attenuation factor θ cannot be evaluated, the interpolation method proposed in the book by Tsividis has been still implemented for Si(100) p-MOSFETs and the results are reported in Table 1.
The four methods have been successfully employed to extract the conduction parameters although a disagreement is visible in regards to the parasitic access resistances Racc. The similarity between the Ciofi method and the Ghibaudo method leads to very similar data and in turn an undervaluation of the parasitic access resistances Racc when compared with the values obtained using the two other methods.
3.2. Silicon wafers with a (110) crystallographic orientation
The extraction methods previously described have been implemented for p-MOSFETs fabricated on (110) silicon-oriented wafers in order to extract the conduction parameters. The results are reported in Table 2, and the extraction methods are consistent. Compared to Si(100) p-MOSFETs, the low field mobility μ0 for Si(110) p-MOSFETs is almost three times higher, confirming the superiority of the hole mobility on (110) silicon surface .
At the same time, the mobility attenuation factor θ is 10 times weaker for Si(110) p-MOSFETs, indicating that the degradation of the effective mobility might be much more pronounced for Si(100) p-MOSFETs. However, the main result is the impossibility to extract the parasitic access resistances Racc and the mobility attenuation factor θ with the Ghibaudo method, whereas the method has been successfully employed for Si(100) p-MOSFETs . Indeed, as shown in Figure 4, whereas the extraction of Gm from Id/gm0.5 has been possible, and in turn the extraction of the low field mobility μ0, the gate length reduction ΔL and the gate width reduction ΔW, the linear fitting of gm−0.5 versus the gate voltage could not be done. Concerning the Schreutelkamp method, the same procedure as previously described has been carried out and a behavior similar to the one noticed for Si(100) p-MOSFETs has been acknowledged.
4. Modeling of the mobility
4.1. Silicon wafers with a (100) crystallographic orientation
The modeling of the hole mobility using Eq. (9) with the data reported in Table 1 (μ0 = 115 cm2/Vs and θ = 0.35 V−1) has been carried out and compared with the experimental data of the effective mobility for Si(100) p-MOSFETs. The result is reported with the dashed line in Figure 5 and demonstrates the great accuracy of the extraction method and of the model provided by Eq. (9) when the effective electric field Eeff is above 0.3 MV/cm. Below this value, the model is inaccurate since the effective mobility is limited by the Coulomb scatterings, scatterings that are not taken into account in Eq. (9). The conduction parameters (μ0 = 115 cm2/Vs, θ = 0.35 V−1, Racc = 70 Ω, ΔL = −0.33 μm, ΔW = −0.13 μm, Vd = 50 mV and W = 20 μm) have been implemented in Eqs. (8) and (9) to model the drain current Id in p-MOSFETs with different gate length L and the transconductance gm has been calculated afterwards. The results are shown in Figure 6 with the thick full lines. At the exception of Vg<Vth, the modeling is greatly fitting the experimental data for either Id or gm. The maximum of the transconductance gm cannot be estimated because Eq. (9) does not model the Coulomb scatterings mechanisms. A second simulation has been calculated without taking into account the parasitic access resistances Racc in Eq. (8), and the results are shown with the dashed line in Figure 6. The fact to neglect the parasitic access resistances Racc leads to a discrepancy between the model and the experimental data that is enhanced when the size of the device is shrinked.
4.2. Silicon wafers with a (110) crystallographic orientation
The modeling of the mobility has been carried out for the Si(110) wafers with the parameters obtained in Table 2. μ0 = 285 cm2/Vs and θ = 0.038 V−1 have been implemented in Eq. (9), and the result is shown with the dashed line in Figure 5 and does not provide a great accuracy like it was the case for Si(100) wafers. Nevertheless, the procedure has been moved forward, and the simulation of the drain current Id and the transconductance gm has been calculated with Eq. (8) and the following parameters: μ0 = 285 cm2/Vs and θ = 0.038 V−1, ΔL = −0.4 μm, ΔW = −0.4 μm and Racc = 60 Ω. The results for the drain current Id are shown with the dashed lines in Figure 7, while the results for the transconductance gm are shown in Figure 8 with the dashed lines. The modeling is accurate at first but strongly divert from the experimental data when the gate overdrive voltage is increased. The use of Eq. (9) does not give at all satisfactory agreement with the experiment, especially concerning the transconductance gm. The well-established model that is Eq. (9) cannot be used to simulate the mobility and thus the drivability of Si(110) p-MOSFETs. Other models [24, 25] have been implemented but did not give enough satisfactory results. Contrary to the (100) orientation for which the single phonon scattering mechanism is limiting the hole mobility over the working range, the hole mobility for the (110) orientation is limited by the Coulomb, phonon and surface roughness scatterings mechanism over the whole measurement range. Thus, a model able to take into account these three mechanisms is required. While Eq. (9), which models only the phonon scattering, is sufficient to simulate the Si(100) p-MOS transistors, a new model including all three scattering mechanisms is needed for the Si(110) wafers.
µCoul = ACoulT−1EeffβCoul  with βCoul ≥ 0 and µsr=AsrEeff−2  are simple ways to model the Coulomb scatterings and surface roughness scatterings, respectively. ACoul and βCoul are constants associated with the Coulomb scattering mechanism, while Asr is a constant associated with the surface roughness scattering mechanism. T is the temperature. Assuming that the effective electric field Eeff is proportional to the gate overdrive voltage Vg – Vth, the dependence of the several scattering mechanisms can be introduced into Eq. (9), which is already modeling the Coulomb scatterings mechanisms to finally give 
μ0 is the low field mobility. θ1 corresponds to the conventional mobility attenuation factor seen in Eq. (9) and is related to the contribution coming from the phonon scatterings. θ2 is a quadratic mobility attenuation factor related to the surface roughness scatterings. α is a parameter related to the Coulomb scatterings, while Aα equals to 1 and is introduced to maintain the uniformity of the unit system. As shown in Figure 6 with the full line, Eq. (10) greatly matches the experimental data. The fitting parameters are as follows μ0 = 280 cm2/Vs, θ1 = 0 V−1, θ2 = 0.05 V−2, and α = 0.04. The simulation of the drain current Id and the tranconductance gm has been carried out for Si(110) p-MOSFETs featuring different gate length by implementing Eq. (10) into Eq. (8). μ0 = 280 cm2/Vs, θ2 = 0.05 V−2, α = 0.04, ΔL = −0.4 μm, ΔW = −0.4 μm, Racc = 60 Ω, Vd = 100 mV and W = 20 μm. The results are reported with the full lines in Figures 7 and 8. The modeling of the drain current Id is greatly accurate even for short gate length. The modeling of the transconductance gm in Figure 8 is also fairly accurate. Both, the results regarding the drain current Id and the transconductance gm testify of the good agreement of Eq. (10). In Figure 8, it seems that the maximum of the transconductance gm, result of α the parameter related to the Coulomb scatterings, can be also calculated. This statement must be taken with care since the maximum of the transconductance is obtained for biases that do not correspond to the linear region, making Eq. (8) obsolete. Actually, the parameter α does not solely reflect the Coulomb scatterings. Indeed, the hole mobility in Si(110) wafers has a peculiar behavior in the form of the inter-subband phonon scatterings. Contrary to the acoustic phonon scatterings that are more and more limiting the mobility with an increase of the effective electric field, the inter-subband phonon scatterings have the specificity to decrease when the effective electric field is increased [21, 28] as sketched in Figure 5.
5. Relation between the mobility, the channel direction and the wafer orientation
Inversion-mode fully depleted p- and n-channel silicon-on insulator (SOI) MOSFETs have been fabricated on bonded SOI (100) and (110) crystallographic silicon-oriented wafers. For each wafer, transistors with different channel directions were manufactured. The process flow has been entirely conducted in the clean room of the Fluctuation Free Facility at Tohoku University. 33-mm-diameter wafers have been used after cutting them from 8 inches wafers. The doping concentration has been adjusted to 1016 cm−3 by ion implantation. The thickness of the SOI layer was 50 nm, and the thickness of the buried oxide was 100 nm. Prior the formation of the 7.5-nm-thick gate oxide by radical oxidation  an alkali-free process [22, 30] able to keep the silicon surface flat was used. The roughness of the Si/SiO2 interface was further reduced by repeating several times the procedure radical oxidation–etching . The procedure has been repeated two times for the Si(100) wafers and four times for the Si(110) ones and led to the same microroughness measured to 0.08 nm. The effective mobility has been measured according to the methodology presented in Section 2 at Vd = 50 mV. Measurements have been carried out on MOSFETs with a gate dimension of W = 100 μm and L = 100 μm.
5.1. Silicon wafers with a (100) crystallographic orientation
The low field mobility μ0, the mobility attenuation factor θ, the gate length reduction ΔL, the gate width reduction ΔW and the parasitic access resistances Racc have been extracted for Si(100) n- and p-MOSFETs and are available in a previous paper by Gaubert et al. . The Ghibaudo and Ciofi methods have been used. Figure 9 shows the effective mobility for hole and electron on Si(100) wafers. It is clear that n-MOSFETs own greater performances than p-MOSFETs since the mobility of the former ones is five times higher than the mobility of the latter ones. It is also clear that the channel direction has no impact on the mobility of the n-MOSFETs. However, a slight difference can be noticed for the hole, the highest mobility being measured for a channel along the <100> direction. The direction of choice for the electronic manufacturers is the <110> direction and an easy and costless way to slightly enhance performances of electronic devices would be to manufacture p-MOSFETs on Si(100) wafers with a channel following the <100> direction. The shift from the <110> direction for the <100> direction can give rise to a maximum enhancement of 10% of the drivability .
5.2. Silicon wafers with a (110) crystallographic orientation
It has been demonstrated in Section 3 that the extraction methods are difficult to set up for p-MOSFETs on Si(110) wafers. Nevertheless, the method proposed by Tsividis has been used for the Si(110) p-MOSFETs while the Ciofi and Ghibaudo method helped extract the conduction parameters for the Si(110) n-MOSFETs. The results are reported in a previous paper by Gaubert et al. . The mobility in Si(110) p-MOSFETs is shown in Figure 10. The dependence with the channel is clearly visible. The highest mobility is obtained for a channel following the <110> direction, while the lowest one is obtained for a channel along the <100> direction. Furthermore, an increase in the mobility with the effective electric field can be noticed, especially for the <110> direction, where an increasing limitation by the phonon scatterings was expected. This behavior is caused by the inter-subband phonon scatterings as noticed in Section 4.2. The clear role played by the inter-subband phonon scatterings on limiting the mobility spans on a more visible way in Figure 10 than in Figure 5. The reason is the lower doping concentration of the devices studied in this section that consequently shifts the Coulomb scattering limited mobility to lower effective electric fields. The inter-subband phonon scatterings are explained by the small energetic separation between the two lowest heavy-hole-like subbands, which is favoring the inter-subband transitions assisted by the absorption of optical phonon. This behavior reaches its maximum for a channel along the <110> direction since the holes in this direction have the lowest mass .
The Id – Vg curves for Si(110) n-MOSFETs have been measured, and the results are presented in Figure 11 along with the corresponding tranconductances gm. The larger drivability is ascribed to the <100> direction. From Ref. , the value of the attenuation factor θ for the Si(100) n-MOSFETs is 0.175 V−1, while the one obtained for the Si(110) n-MOSFETs is 0.6 V−1. The larger value for Si(110) wafers reflects an unusual degradation of the mobility that makes the drain current Id saturate and drop at high gate overdrive voltage Vg – Vth, as shown in Figure 11. The saturation and decrease in the drain current Id are more pronounced for the <100> direction and find its origin in the balance of the linear product (current is proportional to nμ) between the increase in the number of carriers n and the decrease in the mobility μ. As shown in Figure 11, the unusual consequence is a negative transconductance gm at high voltage. The mobility is shown in Figure 12. Like for the Si(110) p-MOSFETs and contrary to the Si(100) n-MOSFETs, there is a dependence between the mobility and the channel direction. The highest mobility is obtained for the <100> direction, and the lowest is obtained for the <110> direction, the opposite trend revealed for Si(110) p-MOSFETs. The surface roughness is limiting in more proportion the mobility of the transistors along the <100> direction and explains the more pronounced drop of the drain current Id shown in Figure 11.
6. Relation between the mobility and the temperature
It is well known that temperature has a major impact on the performances of MOSFETs. Every scattering mechanisms that are limiting the mobility have a specific response toward the change in temperature as Gaubert et al. demonstrated for Si(110) n-MOSFETs . Contrary to p-MOSFETs fabricated on Si(110) wafers, the mobility of n-MOSFETs on this orientation is limited by the Coulomb scattering in the low range effective electric field, the phonon scattering in the middle range and finally the surface roughness scattering at high effective electric field. With the intention to understand the response of each scattering mechanisms taken individually to the temperature, a study has been conducted on Si(110) n-MOSFETs investigated in the precedent section. Transistors with a channel along the <100> direction have been studied for different temperatures from 213 to 473°K. Figure 13 reports the drain current Id and the associated transconductance gm for three different temperatures. Increasing the temperature degrades the drivability and the transconductance even though a slight improvement in the latter quantity can be acknowledged at high gate voltage. In addition, the peculiar behavior acknowledged in the previous section for Si(110) n-MOSFETs, that is a saturation followed by a drop of the drivability with an increase of the gate voltage, is amplified with a decrease of the temperature and leads to even more negative transconductance in the high bias range. This suggests that the drop of temperature increases the degradation ratio generated by the surface roughness scattering mechanisms. The mobility for different temperatures is shown in Figure 14. As expected, the mobility is enhanced when the temperature is reduced. The scattering mechanisms have been studied separately by the means of the modeling. The mobilities shown in Figure 14 have been modeled according the Matthiessen rule with the three main scattering mechanisms:
μCoul is the Coulomb-limited mobility, proportional to Eeffβ where β is a fitting parameter . μPh is the phonon-limited mobility, generally proportional to Eeff−0.3 . Finally, μSR is the surface roughness-limited mobility. It is proportional to Eeffγ  where γ is a fitting parameter generally found between −1 and −3. Quantities ACoul, APh and ASR are fitting parameters associated, respectively, with the Coulomb, Phonon and Surface roughness scattering mechanisms.
The results for the Coulomb scattering mechanisms μCoul are shown in Figure 15. The Coulomb-limited mobility μCoul is temperature dependant, and β is varying between 0.8 and 1.2. A point independent of the temperature is visible for an effective electric field around 3 × 103 V/cm. It corresponds to the crossing point visible on the Id – Vg curves of Figure 13 for Vg around 100 mV. Below that, point the temperature increases the energy of electron that are scattering less since the Coulomb interaction is weakening. Finally, results shown in Figure 15 and those reported by Gaubert et al.  showing an attenuation of the variation of ACoul with a decrease in the temperature suggests that the Coulomb-limited mobility μCoul might become independent of the temperature at low temperature. The results regarding the phonon-limited mobility μPh are shown in Figure 16. The phonon-limited mobility μPh is temperature dependant according to a T−1.3 law. Nevertheless, their ratio with the effective electric field remains unchanged with a change in temperature. The results regarding the surface-roughness-limited mobility μSR are shown in Figure 17. The surface-roughness-limited mobility μSR is temperature dependant. However, like for the Coulomb-limited mobility μCoul, the results at low temperature strongly suggest that the surface-roughness-limited mobility μSR becomes independent when the temperature is lowered down. Gaubert et al.  showed that ASR is converging towards a constant value for temperature lower than 200°K, with γ reaching a value of −2. The surface-roughness-limited mobility μSR features a crossing point for effective electric field around 2 MV/cm, roughly corresponding to the breakdown of the gate oxide. Above this point, the increase in temperature is reducing the collision with the interface. The study of this peculiar behavior is made extremely difficult owing the impossibility to carry measurements on.
To finish, the shift from the Si(100) wafers to the Si(110) wafers degrades the electron mobility as testified by results shown in Figures 9 and 12. The study of the mobility in Si(100) n-MOSFETs has been conducted in a similar way for 303° K exclusively, and the calculation of each scattering mechanisms showed that this degradation is actually the result of a strong limitation arising from the Coulomb and surface roughness scattering rather than the phonon mechanisms, results that has been demonstrated by Gaubert et al. .
7. Mobility in an accumulation layer
Even though making use of the majority carriers to generate the current [36, 37] is already known and has been investigated more than 40 years ago, this approach has recently gained interest, and recent studies have positioned the accumulation-mode MOSFETs as serious competitors [13, 14, 38–41] to take over the conventional transistors for future CMOS technologies. Scarce data have been published so far regarding the carrier mobility flowing inside an accumulation layer [14, 36], and a method to extract it from the conventional mobility measurement is proposed here since in accumulation-mode MOSFETs the conduction, and thus, the measured mobility involves the conduction inside the accumulation layer and the conduction occurring inside the SOI layer. Planar mode fully depleted silicon-on-insulator p-type MOSFETs on three different unibond p-type SOI (100) silicon oriented wafers have been fabricated in order to assess the mobility in an accumulation layer. The doping concentration of the SOI layer has been adjusted to 1015, 1016 and 2 × 1017 cm−3. A 7.5-nm-thick gate oxide has been formed by plasma oxidation after etching the SOI layer until reaching 50 nm. The mobility measurement method proposed in Section 2 has been followed with Qdep = 0. The results are shown in Figure 18. The mobility for the conventional inversion-mode p-MOSFETs has been reported for comparison and accurately follows the universal curve by Takagi et al.  at high effective electric field Eeff. While the results suggest that the mobility for the accumulation-mode devices possessing a doping concentration of 1015 and 1016 cm−3 is following the universal curve, it is clear that the one with a doping concentration of 2 × 1017 cm−3 does not. As expressed previously, the SOI layer is contributing to the total measured current, and in turn, it is included in the calculation of the mobility as presented in Eq. (2). It is also clear from Figure 19 that the calculation of Qacc is false in the case of accumulation-mode MOSFETs. Indeed, the impact of the SOI layer is clearly visible and must be removed to obtain C – Vg characteristics such as the one reported for an inversion-mode MOSFETs in Figure 19.
The appropriate evaluation of the mobility must be conducted from the relevant data, the accumulation charge and the current generated exclusively by the accumulation layer. At the flat-band voltage Vfb, the SOI current reaches its maximum value and its subtraction from the Id – Vg curves give the current generated by the accumulation layer. Vbf is evaluated from the knowledge of the flat-band capacitance Cfb obtained from
where Cdeb is the Debye capacitance and can be easily calculated like Cox. Vfb is obtained with the help of the C – Vg curves shown in Figure 19. By turn, the maximum SOI current and SOI charge are evaluated, respectively, from the Id – Vg and Qacc – Vg curves and subtracted afterwards. The calculation of the effective mobility μeff and of the effective electric field Eeff has been conducted again for the three doping concentration, and the results are shown in Figure 20. All curves are now reaching the universal curve indicating that an accumulation layer has a universal behavior identical to the one seen for an inversion layer. The universal curve by Takagi et al.  is appropriate for both the inversion and accumulation layers. It is also confirming the rightfulness of η = 1/3 for the calculation of the effective electric field Eeff in Eq. (7) indicating again that the carriers in an accumulation layer are behaving in a similar way than the ones in an inversion layer with regard to the phonon and surface roughness scattering mechanisms as previously described by Chindalore et al. . To finish contrary to the inversion layer, an early screening of the Coulomb scattering is occurring in the case of an accumulation layer, allowing the mobility in an accumulation layer to reach at first the bulk mobility before the phonon scatterings dominate [14, 43], thus the monotonically decrease in the mobility seen at low effective electric field Eeff in Figure 20.
These last results indicate that even if the mobility shown in Figure 18 for accumulation-mode MOSFETs with a doping concentration 1015 and 1016 cm−3 could have been interpreted as correct, are actually false owing to the contribution of the SOI layer.
In this chapter, we reviewed some of the main aspects of the mobility in field-effect transistors and especially for the (110) crystallographic silicon-oriented wafers. The mobility in p-MOSFETs on Si(110) wafers is limited by inter-subband scattering mechanism making its extraction by the means of the Ghibaudo method inappropriate and in turn its modeling inaccurate. A more adapted model relying on a physical approach has been developed. This new expression is incorporating the Coulomb, phonon and surface roughness scattering mechanism and is allowing a precise modeling of the drivability and transconductance in Si(110) p-MOSFETs. In addition, the study showed a clear dependency between the mobility and the channel direction for transistors fabricated on Si(110) wafers, while no impact has been noticed for conventional Si(100) wafers. The highest mobility has been revealed for a channel along the <100> direction for electron and along the <110> direction for hole. The study in temperature in Si(110) n-MOSFETs showed that the Coulomb and surface roughness scattering mechanisms are actually temperature dependent. More, the degradation of the electron mobility in Si(110) wafers has been explained by a substantial increase in the Coulomb and surface roughness scatterings than the phonon ones when compared with the Si(100) wafers. To finish, a methodology has been proposed and successfully employed to calculate the carrier mobility in the accumulation layer of newly developed accumulation-mode MOSFETs. The result showed afterwards that accumulation and inversion layers are behaving in a similar way in regard to the phonon and surface roughness scattering mechanism. Nevertheless, the mobility in an accumulation layer is monotonically decreasing from the bulk mobility when the electric field is increased, owing to an earlier screening of the carrier by the Coulomb scatterings.