Open access peer-reviewed chapter

Modeling of Nano-Transistor Using 14-Nm Technology Node

By Soheli Farhana

Submitted: November 8th 2017Reviewed: April 3rd 2018Published: July 18th 2018

DOI: 10.5772/intechopen.76965

Downloaded: 465

Abstract

Latest process technologies in transistor development demonstrate massive changes in the size of transistor chip. In this chapter, a 14-nm technology node is used to model nanosize transistor. The 14-nm technology node consists of multiple numbers of carbon nanotube. Carbon nanotube is a very good energy efficient and low-cost material. Carbon nanotube demonstrates excellent characteristics in metallic and semiconducting characteristics by analyzing electrical properties. At first, the nanotube device physics and material properties are briefly explained in this chapter. Further, a nanotube device is designed for semiconducting properties. The gate length of nanotube is 14 nm which is placed on the gate channel. Finally, the model of 14-nm nano-transistor will be demonstrated for low-energy consumption which can be considered as a better replacement of CMOS.

Keywords

  • nano-transistor
  • 14 nm
  • electrical properties
  • I-V characteristics
  • low energy

1. Introduction

Nanoelectronics research is upgrading due to the increases of consumer demand of electronics device in small scale. Nanotechnology research area encourages the researchers to work on nanomaterials as an immerging technology for future. Carbon nanotube (CNT) is a potential material in the field on nanotechnology that has the ability to overcome almost all the limitations of other nanomaterials for its excellent electrical and mechanical properties. Therefore, one of the potential uses of CNT is to place as gate channel of a FET is called carbon nanotube field effect transistor (CNTFET). Silicon-based circuit is moving towards its physical limitation point according to the proven experiment [1]. Due to similar ballistic transport and high career portability of silicon material, CNTFET can be a good replacement of silicon [2] while CNT can be acted as a semiconducting material [3, 4]. Nanotube is able to show its excellent electrical properties in designing digital devices [5, 6] in small scales. Another special characteristic also to be highlighted for nanotube is I-V features which enable to use the CNT in MOS transistors [7, 8, 9, 10]. According to device physics, the performance of the chip can be improved by reducing the size but there is a limitation about the reduction of silicon device size. Nano-hardware, which was created from the 1990s, has turned out to be a standout amongst the most dynamic research subjects in this day and age. The nanoelectronics innovation, which can fundamentally diminish the transistor measure, is particularly alluring to individuals. Single-walled carbon nanotube is mostly used in transistor [11]. Ballistic transport properties of MOS transistor are unchanged while the gate channel Si is substituted by nanotube [12]. In perspective of the outstanding size-lessening issues of traditional Si-based hardware, there have as of late been serious examinations on new advances in light of nano-organized materials which are shaped by sorted-out development and self get-together strategies. CVD process was used in the laboratory to grow nanotube from dielectrophoresis in early ages of its generation [13]. The first CNTFET was fabricated for prototype testing [14] which allows the researchers to work on this promising field of nanotechnology. CNTFET shows good performance in designing logic gates for integrated circuit modeling [15, 16]. Therefore, CNTFET can be a promising research in the near future.

2. Carbon nanotubes properties

2.1. Geometry of carbon nanotubes

A carbon nanotube can be characterized by chiral vector and its length and a vector called the chiral vector. Chiral vector is the sum of the multipliers of the two base vectors, like Eq. (1) [17, 18, 19, 20]

Ch=ma1+na2E1

The coordinates of the graphene sheet (m,n) allows finding the chiral vector (Ch) of the nanotube.

The two-dimensional graphene lattice in real space can be created by translating one unit cell by the vectors T¯=na¯1+ma¯2with integer combinations (n, m), where a¯1and a¯2are basis vectors and is shown in Figure 1,

a¯1=a032x̂+12ŷa¯2=a032x̂12ŷE2

Figure 1.

The nanotube unit cell.

a0=3accis the length of the basis vector, and acc1.42Å is the nearest neighbor C-C bonding distance.

To all the more decisively acquire the moment vector T, we can get it from the m, n segments of the Ch vector. On the off-chance that we demonstrate the parts of T with t1 and t2, as T is opposite to the Ch, the inward result of these vectors is equivalent to zero and we can conclude Eq. (3)

t1a1+t2a2=0E3

The briefest vector t1 and t2 that are legitimate as per Eq. (3) can be isolated t1 and t2 by their most prominent normal devisor or in short shape most noteworthy basic divisor (gcd), to acquire the briefest nuclear site vector towards the path, opposite to the Ch vector. dR as in Eq. (4), t1, t2 can be accomplished in Eqs. (5) and (6)

dR=gcdm+n2n+mE4
t1=2m+ndRE5
t2=2n+mdRE6

The angle between the chiral vector and the a1 base vector is called the chiral angle, the twist angle or the helix angle and is denoted by θcand can be obtained in Eq. (7)

θc=Arctg3m2n+mE7

Here, we should take note of that to consider a one of a kind chiral plot for each nanotube; the point is expressed by an incentive in the locale (0, 30°). Utilizing these definitions, the breadth of the tube can be processed utilizing the balance of the length of the Ch and the nanotube’s periphery; lastly, we can acquire the measurement characterized by

dt=Lπ=aπn2+nm+m2E8

The length of the chiral vector is the peripheral length of the nanotube:

L=Ch=an2+nm+m2E9

The bandgap of a single wall nanotube (SWNT) is defined by

Eg=2γ0acc/dtE10

From Eq. (4), if (n-m) is divisible by 3, then nanotube is metallic, otherwise the nanotube is semiconducting.

Now, the number of atom of the nanotube is defined by

Nat=4n2+m2+nmdRE11

2.2. Classification of carbon nanotubes

Carbon nanotube (CNT) is classified into three groups as shown in Figure 2: (1) armchair, (2) zigzag and (3) chiral, based on the geometrical arrangements of the graphene during the form tube formation.

Figure 2.

Classifications of different CNTs: (a) armchair, (b) zigzag and (c) chiral (François, 2009).

If the Chis defined as n0, it is given the name zigzag nanotube and if the Chis defined as nn,then the tube is called armchair, and these refer to the form shaped on the circumference of the tube.

2.3. Carbon nanotube formation

2.3.1. Armchair tubes

If the chiral indices (m, n) of a nanotube in a zone-folding region can be divisible by 3, then it becomes metallic. These nanotubes are called ‘zone folding metallic’, or shortly, ZF-M tubes.

2.3.2. Zigzag tubes (semiconducting tubes with bandgap)

The primary band gap of a nanotube is considered as semiconducting material if the Chirality (m, n) in the zone folding area is not divisible by 3. We should allude to these nanotubes as ‘zone collapsing semiconducting’, or in a matter of seconds, ZF-S tubes.

2.4. Electrical properties

Carbon nanotubes (CNTs) have outstanding electrical properties based on the chirality. There are two types of carbon nanotube, such as single-walled carbon nanotube (SWCNT) and multiple-walled carbon nanotube (MWCNT) based on the requirements of the CNT in the integrated circuit (IC) design [21, 22, 23]. Figure 3 shows the different types of carbon nanotube. A single-walled carbon nanotube has only one shell with a small diameter usually less than 2 nm. As well as multi-walled carbon nanotube consists of two or more concentric cylindrical shells with the diameter of 2–30 nm.

Figure 3.

Diagram of carbon nanotube: (a) single-walled and (b) multi-walled (François, 2009).

The electrical properties of a nanotube can be realized from its bandgap. Semiconducting nanotube is a novel choice for the transistor development. Thus, Figure 4 shows bandgap versus radius for semiconducting (zigzag) nanotubes. The bandgap decreases inversely with an increase in diameter. The points with a zero bandgap correspond to metallic nanotubes which satisfy n = 3i, where i is an integer.

Figure 4.

Bandgap versus radius for zigzag nanotube.

3. Modeling process of 14-nm CNTFET

This research consists of the design and verification of the CNTFET device’s small signal model. Figure 5 shows a solid model of CNTFET with a built-in circuit model in this work.

Figure 5.

Perspective view of the CNTFET 3D solid model.

3.1. CNTFET biasing

Three different types of biasing structure are seen in the CNTFET device. They are common-drain, common-gate and common-source structure. Common-source transistor circuit is considered in this modeling. The common-source circuit is shown in Figure 6; the DC shows bias on drain and gate with an AC signal present as the input at the gate.

Figure 6.

Common-source biasing circuit.

3.2. CNTFET small signal model

This section describes about the design and analysis of the small signal model circuit for CNTFET. The proposed small signal model of a CNTFET is shown in Figure 7. In Figure 7, Cg-CNTS refers to the capacitance between gate electrodes to source, Cg-CNTD refers to the capacitance between gate electrodes to drain, Cg-CNTS refers to the capacitance between gate electrodes to source, and Ri represents the internal resistance. Furthermore, gm refers to the intrinsic transconductance and gd refers to the drain conductance of the circuit as shown in Figure 7. In this circuit, the parasitic elements are excluded for the analysis purpose.

Figure 7.

Intrinsic circuit model for CNTFET.

4. Analysis of CNTFET model

4.1. Transconductance of CNTFET SPICE model

Figure 8(a) and (b) shows the simulation results of frequency versus transconductance while the transconductance is increased linearly. This is as a result with μS through the stage of the lower frequency as well as mS through the stage of increasing frequency. Therefore, high-frequency small signal model of CNTFET is obtained in 10 THz with 1.8 mS. On analyzing the data, we first calculate and simulate the transconductance value in μS and in mS.

Figure 8.

Simulation of frequency, fT, versus transconductance, gm: (a) transconductance in μS and (b) transconductance in mS.

Figure 8(a) shows the plot for the value of transconductance in μS and Figure 8(b) shows the plot for the value of transconductance in mS.

Tables 1 and 2 show the selected values of transconductance necessary for the small signal model obtained from the analysis of the model as shown in Figure 8(a) and (b). By comparing the two tables, transconductance in mS performs the higher frequency rather than to use in μS. Therefore, we consider transconductance in mS in this research.

Gm (μS)FT (Hz)
191.0800 × 1011
221.2505 × 1011
281.5915 × 1011
321.8189 × 1011
362.0463 × 1011
452.5578 × 1011
502.8421 × 1011
553.1263 × 1011
603.4105 × 1011

Table 1.

Frequencies for different current gain of small signal model while transconductance in μS.

Gm (mS)FT (Hz)
1.05.68 × 1012
1.16.25 × 1012
1.26.82 × 1012
1.37.39 × 1012
1.58.52 × 1012
1.69.00 × 1012
1.79.66 × 1012
1.810.00 × 1012

Table 2.

Frequencies for different current gain of small signal model while transconductance in mS.

4.2. I-V characteristics of CNTFET

The proposed CNTFET circuit model is implemented in PSpice. A CNTFET DC characteristic is analyzed and simulated to check the output characteristics. Modeling of CNTFET with the I-V characteristics analysis is obtained from the channel length of 14 nm and width of two times the length of the proposed CNTFET. The I-V characteristic curves validate the proposed circuit model by getting drain current of 6.9 × 105 A at the applied gate voltage of 0.4 V as shown in Figure 9.

Figure 9.

I-V transfer characteristics of CNTFET.

4.3. Frequency response of CNTFET

The current gain of the proposed CNTFET is shown in Figure 10. Current gain magnitude is found in 45 dB while the frequency is operated in 10 THz. The value of the CNTFET’s transconductance gm is set as 1.8 mS from the analysis as shown in Figure 10 at the gate voltage of 0.4 V [24].

Figure 10.

Output current gain of the CNTFET at 10-THz frequency.

To validate the output characteristics of the current development of proposed CNTFET, we compare the work with other researches. Table 3 shows the comparison of the performance of the proposed model. From this performance comparison, we would like to conclude that the proposed CNTFET model is capable of operating in high frequency.

Device ParametersCNTFET [25]This Research
Current gain (db)2045
gm (mS)3.81.8
Cgs (F)65f14a
Cgd (F)52f14a
Cut-off-Freq (Hz)30G10T

Table 3.

Comparison of current research.

5. Conclusion

This chapter discussed the development of the CNTFET model using 14-nm technology. We delineated a short examination of the proposed plan of CNTFET little banner show. The arrangement contains a suitable blueprint of the little banner procedure and demonstrated the displays by re-enacting little banner parameters for CNTFET with respect to that of 45 dB. The inherent capacitance of 14 aF and transconductance of 1.8 mS are used as a piece of this examination. A benchmark is showed up for the immense execution of the exhibit made by differentiating and late research data. Particular characteristics are showed up by a course of action of multiplication. Besides, this system has familiar capacitance with survey, the charge defending capacitance at the repeat of 10 THz.

Acknowledgments

The author would like to thank the International Islamic University Malaysia for giving her the opportunity to perform this research.

Conflict of interest

There is no conflict of interest with this publication.

© 2018 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution 3.0 License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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Soheli Farhana (July 18th 2018). Modeling of Nano-Transistor Using 14-Nm Technology Node, Design, Simulation and Construction of Field Effect Transistors, Dhanasekaran Vikraman and Hyun-Seok Kim, IntechOpen, DOI: 10.5772/intechopen.76965. Available from:

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