Open access peer-reviewed chapter

Pole-Zero-Cancellation Technique for DC-DC Converter

By Seiya Abe, Toshiyuki Zaitsu, Satoshi Obata, Masahito Shoyama and Tamotsu Ninomiya

Submitted: October 28th 2010Reviewed: April 7th 2011Published: September 6th 2011

DOI: 10.5772/18590

Downloaded: 5016

1. Introduction

Many types of electric equipments are digitized in recent years. However, the configuration of switch mode power supply is still only analog circuit because the analog circuit is held down to low cost. The digitized system is operated on the basis of a processor. When the switch mode power supply is treated as a part of the system, it is difficult that switch mode power supply inhabit alone in the system as the analog-circuit. Therefore, the digitization of the switch mode power supply is necessary to harmonize with other electronic circuits in the system. So far, various examinations have been discussed about digitally controlled switch mode power supplies[1-5]. However, important parameters such as the switching frequency were impractical because the performance of processor was not so good. Recently, due to the development of the semiconductor manufacture technology, the performance of processor such as DSP and FPGA is developed remarkably. Hence, the expectation of the practical realization in the digitally controlled switch mode power supply becomes higher.

So far, in many case on digitally controlled switch mode power supply, the control system is constructed by very complicated, difficult modern control theory (nonlinear control theory) such as adaptive control or predictive control.

Moreover, also in the most popular and easiest control method such as PID control, the design method is not so clear, and the optimal design is difficult[6, 7].

On the other hand, there are two methods of controller design. One is the digital direct design. The other is the digital redesign. The digital redesign method converts the analog compensator which is designed on s-region into digital compensator. The digital redesign method has some advantages. For example, the control system is designed from classical control theory (linear control theory).

Therefore, many experiences and design techniques of the conventional analog compensator can be utilized. Moreover, from the practical stance, the digital redesign method is more realistic than digital direct design.

This paper investigates the digitally controlled switch mode power supply by means of classical control theory. Especially, the interesting control technique which is cancelled the transfer function of the converter by using pole-zero-cancellation technique is introduced. This technique is very simple and stability design of converter system is very easy. Furthermore, the arbitrary frequency characteristics can be created by introducing a new frequency characteristic. Here, the design method and system stability of the proposed control technique is examined by using buck converter as a simple example.

2. Converter analysis

For the design of the control system, it is necessary to grasp correctly the characteristics of the converter in detail. The buck converter as a controlled object is shown in Fig. 1. The dynamic characteristics of buck converter can be derived by applying the state space averaging method[8,9]. The transfer function of duty to output voltage of buck converter is derived following equation;

Gdv(s)=ΔVo(s)ΔD(s)=Gdvo(s)P(s)E1

where;

P(s)=s2ωo2+s2δωo+1E2
Gdvo(s)=(sωesr+1)RR+rLViE3
ωo=R+rLLC(R+rc)E4

Figure 1.

Synchronous buck converter.

δ=L+C{Rrc+rL(R+rc)}2LC(R+rc)(R+rL)E5
ωesr=1CrcE6

Figure 2 shows the block diagram of analog system. From, Fig. 2, the loop gain of analog controlled converter can be derived following equation;

T(s)=ΔVo(s)ΔVo*(s)=Gdvo(s)P(s)Gc(s)KKsPWME7

where;

Gc(s) : Transfer function of phase compensator

K : DC gain of error amp.

Ks : Sense gain of output voltage

PWM : transfer gain of voltage to duty

Figure 2.

Block diagram of analog system.

In order to evaluate the validity of the analytical result, the experimental circuit is implemented by means of the specifications and parameters shown in Table 1.

SymbolDescriptionValue
ViInput Voltage12V
Vo/IoLoad Condition2.5V/5A
LFilter Inductor22μH
CFilter Capacitor470μF
rLDC Resistance of L100mΩ
rcESR of C10mΩ
RLoad Resistance
KsSense Gain0.32
KFeedback DC Gain5
PWMPWM Gain0.5
fsSwitching Frequency100kHz

Table 1.

Circuit parameters and specifications.

Figure 3 shows the loop gain of the buck converter with p-control in analog control. As shown in Fig. 3, the analytical and experimental results are agreed well. However, as shown in Fig. 4, the big difference is shown in phase characteristics at high frequency side between analog control and digital control.

Figure 3.

Frequency response of loop gain (analog control).

Figure 4.

Frequency response comparison of analog control and digital control (Experiment).

In digital control system, the output voltage as a detected signal is converted to digital signal by AD converter, after that the converted signal is calculated by DSP. Next, the calculated signal decides the duty ratio of next switching period. Hence, the information of the output voltage as the detected signal at certain switching period is reflected into the duty ratio of the next switching period.

Therefore, the dead time element He(s) is included into the control loop as shown in Fig. 5. From Fig. 5, the loop gain of digital controlled system can be derived following equation;

T(s)=ΔVo(s)ΔVo*(s)=Gdvo(s)P(s)Gc(s)He(s)KKsPWME8

where;

He(s)=esTsampleE9

Gc(s) : Transfer function of phase compensator

K : DC gain of error amp.

Ks : Sense gain of output voltage

PWM : transfer gain of voltage to duty

He(s) : Dead time component of digital controller

Tsample : Sampling period

Figure 6 shows the frequency response of dead time element He(s). As shown in Fig. 6, the gain characteristic does not depend on frequency and it is constant.

Figure 5.

Block diagram of digital system.

Figure 6.

Frequency response of dead time element He(s).

On the other hand, phase characteristic depends on frequency. The phase is rotated around 180 degrees at Nyquist frequency (=f/2), and it is rotated around 360 degrees at switching frequency (sampling frequency). From these results, the phase is drastically rotated at high frequency side by the influence of dead time element He(s). In order to evaluate these discussions, the experimental circuit is implemented by means of the specifications and parameters shown in Table 1. Moreover, the experimental result is compared with analytical result. Figure 7 shows the loop gain of the buck converter with p-control in digital control. As shown in Fig. 7, the analytical and experimental results are agreed well. In analog control system, the phase characteristic of frequency response is improved at higher frequency side by the influence of ESR-Zero as shown in Fig. 4, and the system has stable operation.

On the other hand, in digital control system, the phase characteristic of frequency response is drastically rotated by the influence of the dead time element He(s) as shown in Fig. 7. As a result, the phase margin disappears, and the system becomes unstable.

In digital control system, the phase rotation is larger than analog control system by the influence of the dead time element He(s), so the phase compensation is necessary to keep the system stability.

Figure 7.

Frequency response of loop gain (digital control).

3. Conventional phase compensation (Phase lead-lag compensation)

The phase compensation is usually used to improve the system stability. There is various phase compensation. Here, the phase lead-lag compensation is used as the most popular compensation. The digital filter is designed by digital redesign method. The transfer function of phase lead-lag compensation is given by following equation;

Gc(s)=ΔveΔvo*=Kc(sωz1+1)(sωz2+1)(sωp1+1)(sωp2+1)E10

The digital filter can be realized by means of the bilinear transformation.

s=2Tsample1z11+z1E11
Gc(z)=ΔveΔvo*=kz2B2+z1B1+B0z2A2+z1A1+A0E12

where;

k=Kcωp1ωp2ωz1ωz2E13
A0=4Tsample2+2(ωp1+ωp2)Tsample+ωp1ωp2E14
A1=8Tsample2+2ωp1ωp2E15
A2=4Tsample22(ωp1+ωp2)Tsample+ωp1ωp2E16
B0=4Tsample2+2(ωz1+ωz2)Tsample+ωz1ωz2E17
B1=8Tsample2+2ωz1ωz2E18
B2=4Tsample22(ωz1+ωz2)Tsample+ωz1ωz2E19

The determination of the compensator parameter is various. Here, these parameter decide from phase margin. Figure 8 shows the analytical result of loop gain frequency response with phase lead-lag compensation. Where, Kc=10000, fp1=0.03Hz, fz1=1.3kHz, fp2=20kHz, fz2=1.5kHz. As shown in Fig. 8, this system has the stable operation, and then the bandwidth is around 5.5kHz, the phase margin is around 45 degrees. Figure 9 shows the experimental result of loop gain frequency response with phase lead-lag compensation. In this case, the bandwidth is around 5kHz, and the phase margin is around 45 degrees. Moreover, the analytical and experimental results are agreed well. Thus, the observation of control object frequency response is needed in classical control theory (linear control theory).

Figure 8.

Frequency response of loop gain with phase lead-lag compensation (analytical result).

Figure 9.

Frequency response of loop gain with phase lead-lag compensation (experimental result).

Moreover, much experience and knowledge are needed for controller design, because many parameters in compensator should be decided. Therefore, the design method is not so clear and depends on knowledge and experience, and the optimal design is difficult.

The controller design becomes very simple if the controller design is enabled without considering the frequency response of the converter as the control object.

4. Principle of PZC technique

Reduction of the phase rotation is very important for system stability. Especially in the second order system, the phase is drastically rotated around 180 degrees at resonance peak. The stability of the system is improved remarkably if the phase rotation can be reduced.

This paper proposes the control technique which is cancelled the transfer function of the converter power stage by means of pole-zero-cancellation method. The phase rotation and gain change can be suppressed by cancelling the converter power stage characteristics. Furthermore, new characteristic can be designed in the system as the arbitrary transfer function. Figure 10 shows the block diagram of converter system including the pole-zero-cancellation technique.

Figure 10.

Block diagram of digital system with PZC control.

From Fig. 10, the transfer function of compensator part is given following equation;

Gc(s)=Gnew(s)Gpzc(s)E20

The Gnew(s) is the arbitrary transfer function. This transfer function decides the frequency response of converter system. Here, the Gnew(s) is defined as first-order low pass filter.

Gnew(s)=Kcsωc+1E21

In buck converter case, the resonance peak and ESR-Zero are cancelled. The phase rotation of 180 degree is reduced by cancelling resonance peak. The transfer function of the pole-zero-cancellation Gpzc(s) is given following equation;

Gpzc(s)=s2ωo2+s2δωo+1sωesr+1E22

Moreover, the transfer function of the compensator is given following equation;

Gc(s)=Kcs2ωo2+s2δωo+1(sωesr+1)(sωc+1)E23

The digital filter can be realized by means of the bilinear transformation (Eq. 11) as following equation;

Gc(z)=ΔveΔvo*=kz2B2+z1B1+B0z2A2+z1A1+A0E24

where;

k=KcE25
A0=4/ωesrωcTsample2+2(1/ωesr+1/ωc)Tsample+1E26
A1=8/ωesrωcTsample2+2E27
A2=4/ωesrωcTsample22(1/ωesr+1/ωc)Tsample+1E28
B0=4/ωo2Tsample2+4δ/ωoTsample+1E29
B1=8/ωo2Tsample2+2E30
B2=4/ωo2Tsample24δ/ωoTsample+1E31

Figure 11 shows the frequency response of PZC part Gpzc(s). As shown in Fig. 11, the ant resonance peak is appeared at the same frequency of power stage frequency response. Figure 12 shows the analytical result of the loop gain frequency response with PZC technique. Where, Kc=5000, fc=0.01Hz. As shown in Fig. 12, this system has the stable operation, and then the bandwidth is around 400Hz, the phase margin is around 88 degrees. Moreover, the resonance peak and ESR-Zero are completely cancelled, and this system becomes 1st order response. From these results, the converter frequency response is completely cancelled by the influence of PZC part, and the new characteristic is created (1st order characteristic).

Figure 13 shows the experimental result of loop gain frequency response with PZC technique. In this case, the bandwidth is around 400Hz, and the phase margin is around 89 degrees. Moreover, the analytical and experimental results are agreed well.

Figure 11.

Frequency response of PZC part (analytical result).

Figure 12.

Frequency response of loop gain with PZC technique (analytical result).

Figure 13.

Frequency response of loop gain with PZC technique (experimental result).

5. Optimal design of the new transfer function

The first order low pass filter as Gnew(s) is designed for system stability at previous section. Here, the optimization of the Gnew(s) is considered. At first, the stability margin is investigated. In this case, the integrator is included, so the phase starts -90deg. In addition, the phase is shifted by the influence of dead time element He(s) as shown in Fig. 14. Therefore, when the crossover frequency sets to fBW, the phase margin can be derived as follows;

Pm=90360fsfBWE32

When f=fs/4, the phase margin becomes zero.

Next, the gain margin is investigated. In this case, this system has 1st order response, so the slope of gain curve becomes -20dB/dec. Therefore, the gain margin can be derived following equation by using the crossover frequency fBW and fs/4.

Gm=20log10(fs4fBW)E33

From eq. (31), (32), it is clarified that the phase margin and gain margin is automatically decided by the determination of crossover frequency fBW. The Gnew(s) is optimized by means of crossover frequency fBW. The Gnew(s) has two coefficients, ωc and Kc. The coefficient of ωc is decided from Kc and fBW.

The steady state error depends on the output impedance, especially the low frequency component of the closed loop output impedance Zoc. The open loop output impedance can be derived by applying the state space averaging method as following equation;

Zo(s)=s2LCrc+s(L+CrLrc)+rLs2LC+sC(rL+rc)+1E34

Moreover, the closed loop output impedance given from eq. (7) and (33).

Zoc(s)=Zo(s)1+T(s)E35

Therefore, the low frequency component of the closed loop output impedance Zoc can be derived approximately as following equation.

Figure 14.

Frequency response of loop gain with PZC technique for optimal filter design.

Zoc=rLKKsKcPWMVinE36

The steady state error of the output voltage ΔV is given by Zoc product output current variation ΔIo. Therefore, the coefficient Kc can be derived by determining the tolerance of the output voltage variation. From eq. (35), the coefficient of Kc can be derived approximately as following equation.

Kc=rLZocKKsPWMVinE37

Moreover, the total DC gain KDC of loop gain T(s) becomes following equation.

KDC=20log10(KKsKcPWMVin)=20log10(rLZoc)E38

The bandwidth fBW and the coefficient of Kc are decided, and the slope of loop gain is -20dB/dec. From these parameters, the total DC gain KDC can be expressed by using fBW and fc as following equation.

KDC=20log10(fBWfc)E39

From eq. (37), (38), the coefficient of fc is given as following equation.

fc=ZocrLfBWE40

From mentioned above discussion, the coefficients fc and Kc is optimized. Here, the crossover frequency fBW is set to 10kHz. In this case, the phase margin is around 54 degrees and the gain margin is round 8dB. Moreover, the each coefficient is Kc=42, fc=25Hz. Where, the output impedance is set to around 0.25mΩ.

Figure 15 shows the analytical results of the loop gain frequency response with optimal filter design. As shown in Fig. 15, the bandwidth is around 10kHz, the phase margin is around 50 degrees. Figure 16 shows the experimental results of the loop gain frequency response with optimal filter design. In this case, the bandwidth is around 10kHz, the phase margin is around 50 degrees. Moreover, the analytical and experimental results are agreed well.

Figure 15.

Optimal design of loop gain (analytical result).

Figure 16.

Optimal design of loop gain (experimental result).

Next, the transient response of the conventional phase lead-lag compensation and the PZC technique are measured using experimental circuit of 2.5V/5A during the step load transition from 1A to 4A (10A/μs). Figure 17, 18 shows the transient response of the conventional phase lead-lag compensation and PZC technique, respectively. In phase lead-lag comensation case, the output voltage drop is around 320mV and the transient time to the steady state is around 400μs. On the other hand, in the case with PZC technique, the output voltage drop is around 160mV and the transient time to the steady state is around 200μs as shown in Fig. 15, and the transient response is improved.

Figure 17.

Transient response (Phase lead-lag compensation).

Figure 18.

Transient response (PZC technique).

6. Parameter tolerance

Here, the actual system implementation is discussed. So far, Conductive Polymer Aluminum Solid Capacitor (CPASC) is usually used as the output capacitor of low output voltage converter. However, the Ceramic chip capacitor is recently used by the demand of diminution and thinness. The issue of Ceramic chip capacitor is that the capacitance is changed by the applied voltage. Conventionally, the controller is designed by means of power stage frequency response, and it is designed to have some stability margin. However, when the capacitance is changed by the output voltage, the power stage frequency response is changed. Then, the whole system frequency response is changed. Hence, the stability margin is changed, and then the system may become unstable. Moreover, the transient response becomes worse. As a result, prospective performance is not provided.

In order to keep the system stability, it is necessary to understand correctly the characteristics of capacitance variation in detail. Figure 19 shows the experimental measurements of capacitance vs. applied voltage.

The capacitors are used as follows;

Sample 1: CPASC

Nominal value : 470μF

Rated voltage : 10V

Sample 2: Ceramic chip capacitor

Nominal value : 100μF (5 parallel, Total : 500μF )

Rated voltage : 6.3V

As shown in Fig. 19, the capacitance is almost flat in CPASC. On the other hand, the capacitance is drastically changed in Ceramic chip capacitor. In this case, the capacitance variation is around 60%. When the applied voltage is 0V, the capacitance is 410μF, and when the applied voltage is 3.5V, the capacitance is 220μF. As mentioned above, when the capacitance is changed, the system stability is also changed.

Figure 19.

Applied voltage vs. capacitance.

Figure 20 shows the analytical result of stability margin vs. applied voltage. Initially, the stability margin is set “9dB GM and 50deg PM” at CPASC. As shown in Fig. 20, the stability margin is flat for all voltage range at CPASC. On the other hand, the stability margin is reduced when the applied voltage becomes higher. At applied voltage 2.5V, the stability margin is changed form “9dB GM and 50deg PM” to “3dB GM and 25deg PM”. Finally, when the applied voltage is 3.5V, the stability margin becomes limited.

Figure 20.

Applied voltage vs. stability margin.

Figure 21 shows the analytical result of loop gain when the output voltage is 3.5V. Figure 19 has big difference compared with Fig. 15 as an initial condition. As shown in Fig. 19, the anti-resonance peak is appeared at around 1.8kHz. This anti-resonance peak is the influence of Gpzc(s).

Figure 21.

Lop gain with PZC control when capacitance changes (analytical result).

This anti-resonance peak is cancelled by resonance peak of the power stage, essentially. However, the anti-resonance peak is appeared on frequency response because of the power stage resonance peak is shifted by the influence of parameter variation. Moreover, the resonance peak is appeared at around 2.5kHz. This resonance peak is power stage resonance peak.

In this case, the bandwidth is changed from 10kHz to 20kHz, and the stability margin becomes very few. The performance of the system is greatly affected by the parameter variation in this way. Therefore, the parameter tracking is needed to keep the system performance.

There are two methods of parameter tracking. One is perfect tracking method. Another is simplified tracking. The influence of parameter variation is completely cancelled by the perfect tracking method.

However, the accurate detection of the several mV high frequency voltage is very difficult. So, the perfect tracking is not available solution. Here, the simplified tracking method is examined. The data table is used in the simplified tracking method. Figure 22 shows the experimental measurements of capacitance vs. stability margin.

Figure 22.

Capacitance vs. stability margin.

From Fig. 19 and Fig. 22, The designed parameters are listed in Table 2. The auto parameter tracking can be realized by implementation of data table to DSP.

No.Voltage Range (V)Capacitance (μF)
10 - 0.5500
20.5 – 1.0400
31.0 – 1.5350
41.5 – 2.0310
52.0 – 2.5270
62.5 – 3.0240
73.0 – 3.5200

Table 2.

Parameter list.

Figure 23 shows the experimental result of loop gain when the output voltage is 3.5V. As shown in Fig. 23, the anti-resonance peak at around 1.8kHz is reduced. Moreover, the resonance peak at around 2.5kHz is also reduced. In this case, the bandwidth is around 10kHz, and the stability margin is improved. From these results, for parameter tracking, the system characteristics are kept initial conditions.

Figure 23.

Lop gain with parameter tracking.

7. Conclusions

This paper proposes the interesting control technique which is cancelled the transfer function of the converter by means of pole-zero-cancellation technique. This technique is very simple, and easy to stability design of converter system. Furthermore, the arbitrary frequency characteristics can be created by introducing a new frequency characteristic. Especially, optimal design of first-order low pass filter is considered and, the design method and system stability of the proposed control technique is examined analytically and experimentally by using buck converter. Furthermore, the parameter tracking is also examined.

As a result, the effectiveness of proposed control technique is confirmed. Moreover, it is confirmed that the characteristic cancellation of the converter can be realized very easy and can be set the arbitrary characteristic. Furthermore, the effective of parameter tracking is also confirmed.

© 2011 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution-NonCommercial-ShareAlike-3.0 License, which permits use, distribution and reproduction for non-commercial purposes, provided the original is properly cited and derivative works building on this content are distributed under the same license.

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Seiya Abe, Toshiyuki Zaitsu, Satoshi Obata, Masahito Shoyama and Tamotsu Ninomiya (September 6th 2011). Pole-Zero-Cancellation Technique for DC-DC Converter, Advances in PID Control, Valery D. Yurkevich, IntechOpen, DOI: 10.5772/18590. Available from:

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