## 1. Introduction

The electric power transmission grid has been progressively developed for over a century, from initial design of local dc networks in low-voltage levels to three-phase high voltage ac networks, and finally to modern bulk interconnected networks with various voltage levels and multiple complex electrical components. The development of human society and economic needs is the major driving force the revolution of transmission grids stage-by-stage with the aid of innovative technologies. The current power industry is being modernized and tends to deal with the challenges more proactively by using the state-of-the-art technologies in the areas of sensing, communications, control, computing, and information technology. The shift in the development of transmission grids to be more intelligent has been summarized as “smart grid” [see Fig.1].

In a smart transmission network, flexible and reliable transmission capabilities can be facilitated by the advanced Flexible AC Transmission Systems (FACTS), high-voltage dc (HVDC) devices, and other power electronics-based devices. The FACTS devices are optimally placed in the transmission network to provide a flexible control of the transmission network and increase power transfer levels without new transmission lines. These devices also improve the dynamic performance and stability of the transmission network. Through the utilization of FACTS technologies, advanced power flow control, etc., the future smart transmission grids should be able to maximally relieve transmission congestions, and fully support deregulation and enable competitive power markets. In addition, with the increasing penetration of large-scale renewable/alternative energy resources, the future smart transmission grids would be able to enable full integration of these renewable energy resources(Wira et al., 2010, Sauter & Lobashov 2011, Varaiya et al., 2011).

Smart substations would provide advanced power electronics and control interfaces for renewable energy and demand response resources so that they can be integrated into the power grid on a large scale at the distribution level. By incorporating micro-grids, the substation can deliver quality power to customers in a manner that the power supply degrades gracefully after a major commercial outage, as opposed to a catastrophic loss of power, allowing more of the installations to continue operations. Smart substations should have the capability to operate in the islanding mode taking into account the transmission capability, load demand, and stability limit, and provide mechanisms for seamlessly transitioning to islanding operation. Coordinated and self-healing are the two key characteristics of the next generation control functions. These applications require precise tracking of the utility’s phase-angle information, for high performance local or remote control, sensing and fault diagnosis purposes(Froehlich et al., 2011, Han et al., 2009).

On the other hand, the proliferation of nonlinear loads causes significant power quality contamination for the electric distribution systems. For instance, high voltage direct transmission (HVDC), electric arc furnaces (EAFs), variable speed ac drives which adopts six-pulse power converters as the first power conversion stage, these devices cause a large amount of characteristic harmonics and a low power factor, which deteriorate power quality of the electrical distribution systems. The increasing restrictive regulations on power quality problems have stimulated the fast development of power quality mitigation devices, which are connected to the grid to improve the energy transmission efficiency of the transmission lines and the quality of the voltage waveforms at the common coupling points (PCCs) for the customers. These devices are known as flexible AC transmission systems (FACTS) (Fig.2), which are based on the grid-connected converters and real-time digital signal processing techniques. Much work has been conducted in the past decades on the FACTS technologies and many FACTS devices have been practically implemented for the high voltage transmission grid, such as static synchronous compensators (STATCOMs), thyristor controlled series compensators (TCSCs) and unified power flow controllers (UPFCs) (Fig.3), etc(Cirrincione et al., 2008, Jarventausta et al, 2010).

The stable and smooth operation of the FACTS equipments is highly dependent on how these power converters are synchronized with the grid. The need for improvements in the existing grid synchronization approaches also stems from rapid proliferation of distributed generation (DG) units in electric networks. A converter-interfaced DG unit, e.g., a photovoltaic (PV) unit (Fig.4), a wind generator unit (Fig.5) and a micro-turbine-generator unit, under both grid-connected and micro-grid (islanding) scenarios requires accurate converter synchronization under polluted and/or variable-frequency environment to guarantee stable operation of these grid-connected converters(Jarventausta et al., 2010).

Besides, an active power filter (APF) (Fig.6) or dynamic voltage restorer (DVR) (Fig.7) rectifier also requires a reference signal which is properly synchronized to the grid. Interfacing power electronic converters to the utility grid, particularly at the medium and high voltages, necessitates proper synchronization for the purpose of operation and control of the grid-connected converters. However, the controller signals used for synchronization are often corrupted by harmonics, voltage sags or swells, commutation notches, noise, phase-angle jump and frequency deviations(Abdeslam et al., 2007, Cirrincione et al., 2008).

Therefore, a desired synchronization method must detect the phase angle of the fundamental component of utility voltages as fast as possible while adequately eliminating the impacts of corrupting sources on the signal. Besides, the synchronization process should be updated not only at the signal zero-crossing, but continuously over the fundamental period of the signal(Chang et al., 2009, Chang et al., 2010). This chapter aims to present the harmonic estimation and grid-synchronization method using the adaptive linear neural network (ADALINE) (Figs.8 and 9). The mathematical derivation of these algorithms, the parameter design guidelines, and digital simulation results would be provided. Besides, their practical application for the grid-connected converters in smart grid would also be presented in this chapter.

## 2. Mathematical model of the adaptive linear neural network (ADALINE)

The adaptive linear neural network (ADALINE) was used to estimate the time-varying magnitudes and phases of the fundamental and harmonics from a distorted waveform. The mathematical formulation of ADALINE is briefly reviewed. Consider an arbitrary signal*Y*(*t*) with Fourier series expansion as (Simon, 2002):

where *A*_{n} and *φ*_{n} are correspondingly the amplitude and phase angle of the *n*^{th} order harmonic component, and *ε*(*t*)represents higher order components and random noise. In order to formulate the harmonic estimation problem by using ADALINE, we firstly define the pattern vector*X*_{k} and weight vector *W*_{k} as:

The square error on the pattern *X*_{k} is expressed as:

where *d*_{k} is the desired scalar output. The mean-square error (MSE) *ε* can be obtained by calculating the expectation of both sides of Eq. (4), as:

where the weights are assumed to be fixed at *W*_{k} while computing the expectation. The objective of the adaptive linear neural network (ADALINE) is to find the optimal weight vector

where *P*^{T} and *R* are defined as:

Notably, matrix R is real and symmetric, and *ε* is a quadratic function of weights. The gradient function

which is a linear function of weights. The optimal set of weights,

The solution of the Eq. (10) is called Weiner solution or the Weiner filter:

The Weiner solution corresponds to the point in weight space that represents the minimum mean-square error *ε*_{min}. To compute the optimal filter one must first compute R^{-1} and *P*. However, it would be difficult to compute R^{-1} and *P* accurately when the input data comprises a random stream of patterns (drawn from a stationary distribution). Thus, by direct calculating gradients of the square error at the *k*^{th} iteration:

wher*e**e*_{k}=(*d*_{k}-*s*_{k}), and

where the learning rate *μ* is used to adjust the convergence speed and the stability of weights updating process. Taking the expectation of Eq. (12), the following equation is derived:

From Eq. (14), it can be found that the long-term average of *X*_{k} for the same set of weights. The steepest descent search is guaranteed to search the Weiner solution provided the learning rate condition Eq. (15) is satisfied (Simon 2002):

where *λ*_{max} represents the largest eigenvalue of R. As for learning rate *μ*, increasing it results in a faster convergence at the trade-off of losing accuracy and increasing overshoots in transient response. Theoretically, a dynamical learning rate has better convergence characteristic, however, the implementation will be more demanding, and requires more expensive hardware setup. By a trial-and-error approach, a constant learning rate *μ* within the range of 0.025 and 0.04 is found sufficient for adequate stable convergence, which is consistent with Widrow-Hoff delta rule (Chang 2009, Chang 2010, Wira et al., 2010).

When mean-square error *ε* is minimized, the weight vector

Thus the fundamental component of the measured signal *Y*_{1}(*t*_{k})is:

Obviously, the dimension of the weight vector *W*_{k} to be updated depends on the order *N* of the harmonics to be estimated. In case of highly distorted load, lower order structure of neural network is not accurate enough when high convergence speed is required, so using higher order ANN structure is inevitable.

## 3. Synchronization for grid-connected converters using ADALINE technique

This Section formulates the generalized methodology for the phase-locked loop (PLL) design and synthesis by using adaptive linear neural network (ADALINE) technique. The mathematical derivation, the stability analysis and the detailed description of the proposed ADALINE-PLL are outlined consecutively herein. In subsection 3.1, the optimal control parameters selection of the proposed ADALINE-PLL is discussed in terms of the continuous domain and the discrete domain analysis. Furthermore, the time-domain simulation results of the proposed ADALINE-PLL under different control parameters are also presented for verification.

### 3.1. Mathematical formulation of the ADALINE-PLL

This section presents the grid synchronization technique using the ADALINE algorithm. Firstly, the formulation of the ADALINE problem by using single-phase representation is outlined as follows. An arbitrary grid voltage can be represented as:

where *n*th order harmonic component, respectively. Here the *dc* offset is neglected for the sake of brevity. The phase angle of the fundamental component voltage can be expressed as:

where *n*th order harmonic component can be expressed as:

where *n*th order harmonic component. Substituting Eq. (20) back into Eq. (19), rearranging terms, we get:

From Eq. (21), it can be deduced that the original signal denoted by Eq. (18) can be regenerated by adjusting the coefficients *n*=1, …, N), even though the phase angle of the original signal is unknown. The objective of the proposed ADALINE-PLL is to reconstruct the phase information of the fundamental grid voltage *W* is denoted by the coefficients of the corresponding trigonometric functions. Followed by this idea, Eq. (21) can be expressed as:

where *W* and *X* corresponding to the weight vector and the input vector, respectively, are represented as:

Equation (23) can be rewritten as:

Notably, the salient difference between the ADALINE algorithm and the ADALINE-PLL algorithm is that, the frequency and phase angle signals utilized in the ADALINE weights updating process were assumed to be constant. However, in case of the ADALINE-PLL, the frequency and phase angle of fundamental component grid voltage is recursively updated by the loop filter (LF) and voltage controlled oscillator (VCO) of the PLL. In other words, the weights updating procedure of the ADALINE is utilized as the phase detector (PD) for the PLL, which generate the error signal to drive the loop filter (LF) and voltage controlled oscillator (VCO), according to the initial definition of PLL The graphical interpretation of the proposed ADALINE-PLL is illustrated in Fig.9. In order to better illustrate the working principle of the proposed ADALINE-PLL, the weights updating law and stability conditions are discussed in detail as follows.

In the discrete domain, the weight vector of the ADALINE should be changed in a minimum manner, subject to the constraint imposed on the updated filter output. Let *k*th iteration and *k*+1)th iteration. Therefore, given the input vector

For each (*X*_{k}, *Y*_{k}) pair, there exist at least one

Hence the weights adaption process is achieved by solving the optimization problem, as indicated by Eqs. (26)-(27). The cost function at the *k*th iteration can be formulated by using the method of Lagrange multipliers (Wira et al., 2010, Yin et al., 2010), as:

where

The optimum weight vector can be found by minimizing the cost function

By setting Eq.(30) equal to zero, the optimum value for

Hence, the output of the ADALINE as denoted by Eq. (22) can be rewritten as:

Then, the Lagrange multiplier

where

In order to ensure stable operation of the weight vector updating process, a positive real scaling factor *μ* (learning rate) is introduced to the step size. Hence Eq. (34) can be redefined as:

Equivalently,

The aforementioned weights updating scheme, in essence, belongs to the well-known least mean square (LMS) algorithm, which may introduce convergence problem in case of small input vector

where

### 3.2. Stability analysis of the ADALINE

The selection of the step-size parameter *µ* is a compromise between the estimation accuracy and the convergence speed of the weights updating process. Generally speaking, a higher step-size would result in faster dynamic response and wider bandwidth of the ADALINE-PLL. On the other hand, if the step-size is selected too small, the corresponding ADALINE would be slow in transient response and results in a narrow bandwidth in frequency domain. Assuming that the physical mechanism responsible for generating the desired response *Y*_{k} is controlled by the multiple regression model:

where *W* represents the model’s unknown parameter vector and *W*, hence the estimation error can be presented by:

From Eqs.(37)-(39), the incremental in the estimation error can be derived as:

As stated above, the underlying idea of the ADALINE design is to minimize the incremental change in the weight vector *k*th and (*k*+1)th iteration, subject to a constraint imposed on the updated weight vector

Taking the squared Euclidean norms of both sides of Eq. (41), rearranging terms, and then taking the expectations on both sides of equation, we get:

where

From Eq.(43), it shows that the mean-square deviation

Considering the limited rate of variation in parameters for the practical grid-connected converter applications, if faster adaptation for the weight vector

### 3.3. Description of the proposed ADALINE-PLL

Figs.10-11 show the single-phase and three-phase version of the proposed ADALINE-PLL. The following discussion is mainly focused on the single-phase version of the ADALINE-PLL, but the similar analysis can be easily extended to the three-phase version. For the sake of brevity, only the fundamental component, fifth and seventh order harmonics are considered in the grid voltages, hence the estimation blocks corresponding to these three components are considered in the single-phase ADALINE-PLL. One may extend the order of the ADALINE-PLL by incorporating higher order harmonic blocks in the algorithm according to the particular applications. Fig.10(a) shows the top layer representation of the single-phase ADALINE-PLL, it can be observed that the estimation error, phase angle of the fundamental component in grid voltage, the learning rate are utilized as the input signals to the subsystems, namely, the fundamental frequency block, the fifth order harmonic block and the seventh order harmonic block.

Figs.10(b)-(d) shows the three subsystems for individual harmonic component estimation, namely, the fundamental component, the fifth and the seventh order harmonic components. Once again, the weights of the fundamental frequency component are denoted as

The derived signal

Fig. 11 shows the corresponding three-phase version of the proposed ADALINE-PLL, which has a similar architecture with that of the single-phase version. One of the salient features of the three-phase ADALINE-PLL algorithm is that the Clark’s transformation and Park’s transformation are utilized consecutively to derive the *q*-axis component of the grid voltages, similar to the procedure adopted in the conventional three-phase PLL (CPLL) and the virtual PLL (VPLL). However, the adaptive linear optimal filter (ADALINE) is used as the phase detector (PD) section, which generate the *dc* component for the voltage controlled oscillator (PI regulator). It should be noted that there is one fundamental frequency shift when the electric quantities are transformed from the stationary *α*-*β* reference frame to the synchronous rotating reference frame (*d*-*q* frame). Besides, it is well known that the typical balanced nonlinear load produce characteristic harmonics of the orders: -5, +7, -11, +13… 6*n*+1 (*n* is integer), corresponding to the 6*n*th order harmonic components in synchronous rotating reference frame. Therefore, the 2^{nd} order harmonic in Fig.11 corresponds to the fundamental frequency negative sequence component, while the 6^{th} order harmonic corresponds to the 5^{th} order harmonic (negative sequence) and the 7^{th} order harmonic (positive sequence) in stationary phase a-b-c frame. Generally speaking, the harmonic components considered in the proposed ADALINE-PLL are selected according to the particular applications and the available computational resources.

### 3.4. Parameter selection of the ADALINE-PLL

In this section, the parameter design of the single-phase version ADALINE-PLL is discussed by using continuous domain (*s*-domain) analysis, discrete domain (*z*-domain) analysis and time-domain simulation. It is found that the proposed ADALINE-PLL has the characteristic of band-pass filter around the fundamental frequency and a notch filter at harmonic frequencies.

#### 3.4.1. Continuous-domain (s-domain) analysis

Assuming the phase angle of the fundamental grid voltage detected by the closed-loop ADALINE-PLL is denoted by

where

where

where *μ*) of the weights updating process (*μ=k*_{1}*T*). Combining Eq.(47) and Eq.(48), we get

Similarly, for the *n*th order harmonic block in Fig.12, the generalized transfer function from estimation error

For the present case, the fundamental component, fifth and seventh order harmonics are considered, hence the error transfer function from the input

Similarly, the transfer function from the input

Fig. 13 shows the bode-plot of the ADALINE when only the fundamental frequency block is considered. The frequency response of the ADALINE under the variations of the center frequency *μ*), has a significant effect on the frequency characteristics of the ADALINE. Small learning rate results in a sharp amplitude-frequency curve and steep phase-frequency curve. Besides, small learning rate implies a narrow bandwidth and slow transient response of the weights updating process. Higher learning rate, on the other hand, implies a flat amplitude-frequency curve, which would improve the dynamic response, increase the bandwidth of the ADALINE.

Fig.14 shows the frequency response of the ADALINE when the fundamental component, fifth and seventh harmonic components are considered. Fig.14(a) shows the bode-plot from the input signal *V*_{sa}(*s*) to the estimation error *E*(*s*). It can be observed that it exhibits as a typical notch filter, and significant attenuation is observed in the amplitude-frequency curve at the harmonic components under consideration. The attenuation at particular harmonic frequency is controlled by the selection of the learning rate of ADALINE, higher learning rate implies higher attenuation. Fig.14(b) shows the bode-plot from the input signal *V*_{sa}(*s*) to the estimated fundamental component *V*_{sa1}(*s*). It can be observed that it exhibits a band-pass filter around the fundamental frequency, and a notch filter at the considered harmonic frequencies. In case of large frequency variation in grid voltages, the learning rates of the ADALINE should be sufficiently high to ensure a wide bandwidth. Besides, it should be noted that the number of harmonics considered in the ADALINE-PLL can be easily extended to higher order harmonic components according to the particular applications.

It should be noted that the frequency domain analysis is based on the quasi-steady state model of the ADALINE, which serves the purpose of phase detection (PD) for the PLL. The estimated phase error signal is then utilized as the input for the loop filter (LF), which is selected as the standard proportional-integral (PI) regulator for the present case. Here the linearized model for the phase estimation can be described as Fig.15(a). It is interesting to observe that the derived linearized model for the phase estimation resembles that of the existing PLL algorithms. The closed-loop transfer function of the linearized model indicated by Fig.15(a) can be represented as:

where

where *k*_{p} and *τ* denote the proportional gain and time constant of the PI regulator, and the integrator gain *k*_{i}=*k*_{p}/*τ*. Equation (54) can be rewritten in the generalized second order system as:

where

The open loop transfer function of Fig.15 (a) can be derived as:

The root locus for the PLL modeled in the *s*-domain is shown in Fig.15(b). There are two open loop poles at the origin of the *s*-plane and one open loop zero at *s*=-1/*τ*. However, it is interesting to notice from Fig.15(b) that the *s*-domain model never predicts an unstable mode for any combination of PI parameters. Therefore, the discrete domain (*z*-domain) would be necessary to study the stability characteristic of the proposed ADALINE-PLL, as discussed in subsequent section.

#### 3.4.2. Discrete-domain (z-domain) analysis

In the discrete domain, Eq. (50) can be rewritten as:

where *T* is the sampling frequency specified according to the particular applications, for the present case, *T*=100μs is selected which is the typical sampling frequency for the low voltage power converters. Hence, the discrete domain transfer function from

Assuming that *T*=100μs, and the integration gain *k*_{n} of individual harmonic component are assumed to be identical for the sake of simplicity (*k*_{n}=*K*), then the following representation can be derived:

The root locus for the ADALINE modeled in the *z*-domain is shown in Fig.16. There are two open loop zeros at *z*=1, a pair of conjugate zeros and three pair of conjugate poles distributing in the z-plane. It can be observed from Fig.16 that the stability margin increases with the increase of integration gain K when 80<K<554 (0.008<µ<0.055) and decreases with the increase of K when 554<K<6833 (0.055<µ<0.68). Moreover, it can be observed from the root locus diagram that when 80<K<6833 (0.008<µ<0.68), the ADALINE system is stable, otherwise it is unstable.

The ADALINE subsystem is assumed to be stable in the following discrete domain analysis, which implies that the phase detection is achieved. The *z*-domain analysis will be performed on a discrete-time PLL system with a second-order loop filter. As shown in Fig.17(a), and the block *K*_{d}(z) is the *z*-transform of the loop filter and voltage-controlled oscillator (VCO), hence the closed-loop transfer function can be represented as:

For the second order loop using the PI type filter, *K*_{d}(*z*) can be obtained as

where *T* denotes the sampling period of the discrete system. The transfer function of the closed loop system in the discrete-time domain can be derived by substituting Eq. (61) into Eq. (60) as

where

The root locus for the PLL modeled in the *z*-domain is shown in Fig.17(b). It can be observed that there are two open loop poles at *z*=1 and two open loop zeros at *z*=0 and *z*=*α*. It is interesting to note that, since the open-loop zero location (*α*) is a function of the time constant *τ*, the z-domain model can predict unstable loop performance for the condition of *α* is located on the negative real axis outside the unit circle. For *α* is close to unity, in this case, the *z*-domain and *s*-domain model predict similar characteristics for jitter[1] - frequencies within the loop’s bandwidth. Moreover, the selection of parameter *k*_{p} is a tradeoff between loop’s bandwidth and dynamic response.

### 3.5. Time-domain simulation results of the ADALINE-PLL

Figs.18-19 show the time-domain simulation results of the single phase version of the proposed ADALINE-PLL under different control parameters. The grid voltage is assumed to contain 0.1 p.u. 5^{th} order harmonic and 0.1 p.u. 7^{th} order harmonic components and a transient voltage sag occurs at t=0.05s to test the dynamic response of the ADALINE-PLL. Fig.18 shows the performance of the single-phase ADALINE-PLL with the variation of learning rate (*μ*) when the loop regulator gains are selected as:*k*_{p}=300, *k*_{i}=10000. It can be observed that if the learning rate is selected too small, the estimation error of the ADALINE-PLL would be remarkable and there would be significant oscillation in the estimated frequency and the phase estimation error (see the dash line and the dash dot line in Fig.18). The solid line in Fig.18 shows the performance of the ADALINE-PLL corresponding to the optimal learning rate *μ*=0.035.

Fig.19 shows the performance of the ADALINE-PLL with the variation of regulator gains when the learning rate is predefined. It can be observed that the dynamic response of the ADALINE-PLL is mainly determined by the proportional gain *k*_{p}, if *k*_{p} is selected too small, the ADALINE-PLL becomes sluggish and the estimated frequency and phase error decays slowly (dash line in Fig.19). On the other hand, if the gain is selected too high, there would be large overshoot in the estimated frequency and the phase estimation error (the dash dot line in Fig.19). It should be noted that the performance of the ADALINE-PLL is less sensitive to the integration gain *k*_{i}*.* The solid line in Fig.19 shows the performance of ADALINE-PLL corresponding to the optimal regulator parameters.

## 4. Performance comparison with the existing PLL algorithms

This section presents the performance comparison among the existing PLL algorithms and the proposed ADALINE-PLL. Firstly, a brief introduction of the enhanced PLL (EPLL) and the *park*-PLL is presented. Then, the simulation results of these algorithms are compared with those of the ADALINE-PLL under grid voltage disturbances, such as grid voltage sag, harmonics and random noise contamination scenarios.

### 4.1.The enhanced phase-locked loop (EPLL)

In recent literature, the enhanced PLL (EPLL) system was proposed (Karimi-Ghartemani et al, 2004). The major improvement introduced by the EPLL is in the PD mechanism, which is replaced by a new strategy allowing more flexibility and provides more information such as amplitude and phase angle. The mechanism of this EPLL is based on estimating in-phase and quadrature-phase amplitudes of the desired signal, hence, has potential application in communication systems which employ quadrature modulation techniques.

The Matlab/Simulink diagram of this EPLL is shown in Fig.20. It can be observed that there are three gains, denoted as *k*_{g}, *k*_{p} and *k*_{i}, which are selected to control the convergence speed for the amplitude, phase and frequency of the fundamental component of the input signal. The guideline for the selection of these gains, however, is not that trivial. The control loop interaction exists since the amplitude, phase and frequency estimation are competing with each other, if any of these gains is varied, it would affect the performance and stability of the closed-loop algorithm. Generally, the gain for the frequency estimation (*k*_{i}) should be very small to ensure stability. However, it would result in slow dynamic performance under frequency deviation in the grid voltage. If the frequency estimation is disabled by setting *k*_{i}to be zero, steady state error may appear or the algorithm may even diverge under large deviations in the input. Therefore, this EPLL scheme is difficult to be practically implemented, especially for the grid-connected converters which has demanding requirements for tracking accuracy, stability and reliability of the synchronization algorithm (Karimi-Ghartemani et al, 2004).

### 4.2. The *Park* phase-locked loop (*Park*-PLL)

The *park*-PLL was another single-phase version of the three-phase synchronous reference frame (SRF) PLL (Filho, R. M. S., et al., 2008). As shown in Fig.21, the circuit diagram of the *park*-PLL consists of two matrix transformations, namely, the Park’s transformation and the inverse Park’s transformation. The component *v*_{β} of the stationary frame is obtained by inverse Park’s transformation of the filtered synchronous components *τ*_{d} and *τ*_{q} of the two first-order low pass filters (FOLPFs) determines the dynamic characteristics of the phase detection (PD) section.

It was reported that the PD is always asymptotically stable around the equilibrium condition *τ*_{d}(or*τ*_{q}) is made too small, a pair of real poles will take place and results in a slow dynamic response. On the other hand, if*τ*_{d}(or*τ*_{q}) is made too high, a pair of complex conjugate poles with small real part will take place, which makes the *park*-PLL slow and oscillatory. It was suggested that the filter cutoff frequency should be equal to about two times line frequency to ensure a fast dynamic response (Filho, R. M. S., et al., 2008).

After the cutoff frequency of the low pass filters is selected, the compensator gains, namely, *k*_{p} and *k*_{i}, can be set in order to meet dynamic response and line disturbance rejection specifications. However, it should be noted that each harmonic component of order *h* and amplitude *V*_{h}in input grid voltage will produce two components of orders *h*±1 and amplitude of *V*_{h}/2 in the PD output. Besides, a *dc* component in input voltage will also lead to a fundamental frequency oscillation in the *dq* components. Therefore, a tradeoff between speed of dynamic response and harmonic rejection capabilities should be achieved to optimize the performance of the *park*-PLL.

### 4.3. The performance evalution among the EPLL, the *Park*-PLL, and the ADALINE-PLL

Fig.22 shows the simulation results corresponding to the estimated frequency in grid voltage and the phase estimation error when the grid is subjected to 0.7 per unit (p.u.) voltage sag. Here the existing grid synchronization schemes, namely, the enhance PLL (EPLL) and the *park*-PLL are also simulated for the sake of comparison. It can be observed that the *park*-PLL and the EPLL have similar dynamic response in the estimated frequency, with an overshoot of 5Hz when voltage sag occurs. It is interesting to notice that the response time of *park*-PLL and the EPLL is longer when the grid voltage recovers to normal condition. The proposed ADALINE-PLL shows the lowest frequency overshoot compared with other grid synchronization schemes. As far as the phase estimation error is concerned, the phase estimation error of the *park*-PLL and EPLL has high transient overshoot with noticeable oscillations. Whereas, the proposed ADALINE-PLL shows the best dynamic response with smallest phase estimation error with overshoot of about 2 degrees. It can be concluded from the estimated frequency and the phase estimation error that the ADALINE-PLL provides a more robust performance when subject to significant sag in the grid voltage.

Fig.23 shows the simulation results corresponding to the estimated frequency in grid voltage and the phase estimation error when the grid is contaminated by harmonics. The 0.3 per unit (p.u.) 5th order harmonic and 0.3 per unit (p.u.) 7th order harmonic components are added to the grid voltage at t=0.05s with a duration of 0.15s to test the immunity of the various grid synchronization schemes. The *park*-PLL and the EPLL show noticeable oscillations in the estimated frequency when the harmonics are added to the grid voltage. Besides, the *park*-PLL shows longer settling time when the grid voltage recovers to the normal condition. The EPLL shows the highest estimation error in grid frequency with amplitude of about 20 Hz, and the *park*-PLL shows the estimation error of about 10Hz when the harmonics are imposed. However, the proposed ADALINE-PLL shows the lowest frequency overshoot (0.5Hz) and highest estimation accuracy in the estimated frequency compared to the other grid synchronization schemes. Furthermore, the phase estimation error of the *park*-PLL and the EPLL is remarkable during transients, and the *park*-PLL is found to have a large settling time when the grid voltage recovers. Besides, it shows that the EPLL has significant ripples in the phase estimation error. However, the proposed ADALINE-PLL shows negligible estimation error compared to the other algorithms, which implies that the proposed ADALINE-PLL shows better robustness under harmonic contamination in grid voltages.

Fig.24 shows the simulation results corresponding to the estimated frequency in grid voltage and the phase estimation error when the grid voltage is contaminated by random noise. The random noise of power density 10e-5 per unit (p.u.) is added to the grid voltage at t=0.05s with a duration of 0.15s to test the immunity of the various grid synchronization schemes. Similar to the case of a sudden applying harmonics, the park-PLL and EPLL show noticeable oscillations in the estimated frequency when the noise is added to the grid voltage. Besides, the park-PLL shows longer settling time when the grid voltage recovers to the normal condition. The EPLL shows the highest estimation error in grid frequency with amplitude of about 5 Hz, and the park-PLL shows the estimation error of about 2Hz when the noise is imposed. However, the proposed ADALINE-PLL shows the lowest frequency oscillation (0.2Hz) and highest estimation accuracy in the estimated frequency compared to the other grid synchronization schemes. Moreover, the phase estimation error of the park-PLL and the EPLL is remarkable during transients, and the park-PLL is found to have a large settling time when the grid voltage recovers. Besides, it shows that the park-PLL has the maximum phase estimation error of about 3 degrees, and the phase estimation error of EPLL is less than 2 degrees. However, the proposed ADALINE-PLL shows negligible estimation error compared to the other algorithms, with amplitude of less than 0.5 degree. The estimated frequency and the phase estimation error in Fig.24 indicate that the proposed ADALINE-PLL shows better robustness when grid voltage is contaminated by random noise.

## 5. Conclusions

The electrical power systems are under a transition to the smart grid owing to the advancement of modern control, communication technologies and the requirement of real-time marketing. In the smart grid, the power converters are indispensable components which connect the renewable energy resources and the FACTS devices, power quality conditioning devices to the grid. Hence the accurate grid-synchronization of these power converters to the grid is crucial to ensure their stable operation. This book chapter aims to provide a systematic approach for the adaptive linear neural network (ADALINE) algorithm for the real-time harmonic estimation and phase synchronization for the grid-connected converters, which are the fundamental building blocks for the smart grid infrastructure.

The mathematical derivation of the ADALINE algorithm and the ADALINE-PLL scheme is presented, followed by the stability analysis, the continuous domain and the discrete domain models, and the guidelines for parameter selection of the ADALINE-PLL algorithm. The performance of the ADALINE-PLL is further validated by performance comparison with the existing park-PLL and EPLL algorithms. It can be expected that the presented ADALINE-based algorithms can find wide application in the grid-connected converters for smart grid applications.

## Acknowledgment

This work is financially supported by the Fundamental Research Funds for the Central Universities of China under grant No.ZYGX2011J093.

## Notes

- www.mathworks.com
- Jitter—The time variation of a characteristic of a periodic signal in electronics and telecommunications, often in relation to a reference clock source.