Electrical and Thermal Properties of Cell Materials.
1. Introduction
Nowadays, non-volatile storage technologies play a fundamental role in the semiconductor memory market due to the widespread use of portable devices such as digital cameras, MP3 players, smartphones, and personal computers, which require ever increasing memory capacity to improve their performance. Although, at present, Flash memory is by far the dominant semiconductor non-volatile storage technology, the aggressive scaling aiming at reducing the cost per bit has recently brought the floating-gate storage concept to its technological limit. In fact, data retention and reliability of floating-gate based memories are related to the thickness of the gate oxide, which becomes thinner and thinner with increasing downscaling. The above limit has pushed the semiconductor industry to invest on alternatives to Flash memory technology, such as magnetic memories, ferroelectric memories, and phase change memories (PCMs) (Geppert, 2003). The last technology is one of the most interesting candidates due to high read/write speed, bit-level alterability, high data retention, high endurance, good compatibility with CMOS fabrication process, and potential of better scalability. However, it still requires strong efforts to be optimized in order to compete with Flash technology from the cost and the performance points of view.
In PCMs, information is stored by exploiting two different solid-state phases (namely, the amorphous and the crystalline phase) of a chalcogenide alloy, which have different electrical resistivity (more specifically, the resistivity is higher for the amorphous, or RESET, phase and lower for the crystalline, or SET, phase). Phase transition is a reversible phenomenon, which is achieved by stimulating the cell by means of adequate thermal pulses induced by applying electrical pulses. Reading the resistance of any programmed cell is achieved by sensing the current flowing through the chalcogenide alloy under predetermined bias voltage conditions. The read window, that is, the range from the minimum (RESET) to the maximum (SET) read current, is considerably wide, which allows safe storage of an information bit in the cell and also opens the way to the multi-level approach to achieve low-cost high-density storage. ML storage consists in programming the memory cell to one in a plurality of intermediate resistance (i.e., of read current) levels inside the available window, which allows storing more than one bit per cell (the number of bits that can be stored in a single cell is
In this work, we investigate the impact of technology scaling down on both the program and the read operation by means of a simple analytical model which takes the electro-thermal behavior of the PCM cell and the phase change phenomena inside the chalcogenide alloy into account.
2. Working principle of the PCM cell
The working principle of a PCM cell relies on the physical properties of chalcogenide materials, typically
The typical V-I characteristic of the PCM cell in the amorphous (RESET) and the crystalline (SET) state is shown in Fig. 2. Consider the case of a cell in its full-SET state: the differential resistance of the cell decreases as the applied voltage increases. This effect is due to the contribution of the crystalline GST to the cell resistance. In fact, the crystalline GST resistivity decreases with increasing electrical field inside the material.
The V-I curve of the cell in its RESET state shows an S-shaped behavior. This effect is due to the threshold switching phenomenon (Adler et al., 1980; Ovshinsky, 1968; Pirovano et al., 2004; Thomas et al., 1976) which consists in a sudden drop of the amorphous GST resistivity as the voltage across the PCM cell exceeds a critical value, typically referred to as threshold voltage,
A PCM memory chip is made of a large number of PCM cells organized in a bi-dimensional array. As opposed to the case of Flash memories, in which the elementary storage consists of a floating-gate transistor, the PCM memory cell is a programmable resistor and, hence, is a two-terminal device. For this reason, a NOR type architecture is adopted (Fig. 4a). As shown in Fig. 4b, each memory cell consists of a PCM storage element connected to a selection transistor
3. Programming operation
We analyzed first the impact of technology scaling on the programming operation, focusing our attention on the electical power (hereinafter referred to as programming power). The maximum programming power is obviously required by the RESET operation, where the highest temperatures are needed to melt the active GST volume. The RESET pulse duration must be higher than the minimum required time for melting \cite{Weidenhof00}, while the cooling time must be short enough to prevent the crystallization process from taking place. The minimum current required to melt a portion of the active GST layer is referred to as melting current,
The maximum temperature reached inside a Lance heater cell of given sizes can be estimated by means of an approximated electro-thermal model. In general, the temperature increase in the active GST volume is due to the current flow both through the heater (heater heating) and through the GST layer itself (GST self-heating). Nevertheless, GST self-heating can be neglected when considering high-amplitude RESET pulses. In fact, the resistance of the GST layer (both in the crystalline and in the amorphous state) is negligible with respect to the heater resistance due to high-field effects (the PCM cell is operated in the ON region). Thus, in this case we can estimate the temperature profile inside the PCM cell by considering only the Joule power generated inside the heater when a current
where
By integrating Eq. (1) along the cell axis from the BEC-heater contact (
In the above equations,
From Eq. (2), taking the expression of
In order to estimate the dependence of
As highlighted by Eq. (5), the melting current depends on the ratios
Due to fabrication process constraints, heater geometries with a high aspect ratio (i.e., geometries having a high ratio between the GST-heater contact diameter and the heater height), may not be easily manufacturable. Several fabrication solutions have been proposed to overcome lithographic limits and, thus, realize heater structures with minimized contact area (Lam, 2006; Pirovano et al., 2008). In the following, we will consider heater geometries with a high aspect ratio with the purpose of investigating the scaling perspective, even if they may require advanced fabrication techniques. Given a scaling factor < 1,
In order to compare PCM cells having different dimensions, we chose to consider the full- RESET state to be achieved when the maximum temperature inside the PCM cell reaches a
predetermined value,
The values of the electrical and thermal properties used in the above simulations are summarized in Tab. 1. For simplicity, the field dependence of the crystalline GST resistivity was neglected. In order to validate the described analytical compact model, we compared the temperature profiles along the cell axis obtained with this model and our 3D finite-element model (Fig. 9).
Heater thermal conductivity | Kh | 36 |
GST layer thermal conductivity | KGST | 0.5 |
Heater electrical resistivity | Ph | 30 µƱ m |
Cryst. GST electrical resist. | PC | 0.1m Ʊ m |
Amorph. GST electrical resist. | PA | 10m Ʊ m |
A good agreement is observed especially inside the GST layer. The slight temperature disagreement inside the heater is ascribed to the inhomogeneous heat flow in the material that surrounds the heater. To take this thermal evacuation contribution into account, the value of
4. Read operation
The GST layer undergoes crystalline to amorphous phase transition in the region where the temperature exceeds the melting point. As pointed out above, the temperature profile along the cell axis inside the GST decreases almost linearly with the distance from the GST-heater interface. By approximating the thermal profile inside the GST along the cell axis with a straight line, we derived the analytical expression for the thickness of the amorphous cap
Thus, the thickness of the amorphous cap obtained by means of the RESET operation is a fraction
where
In order to estimate the cell resistance in the full-SET state, by neglecting the current spread inside the crystalline GST, we can write:
where
When considering the current sensing approach, we can calculate the minimum and the maximum read current:
where
where
Several studies (Adler et al., 1980; Buckley & Holmberg, 1974) have shown that
It can be noticed from the simulation results in Fig. 10, that constant voltage approach leads to an increase of the SET read current as the thickness of the GST layer decreases, due to the reduction of the SET resistance. Moreover, a significant increase of the minimum current (RESET state), mainly due to the dependence of amorphous GST resistivity on the electrical field, is apparent. The increase of the RESET read current depends on
field scaling. In this case, the current read window scales as shown in Fig. 11. The RESET current is almost independent on
5. Conclusions
In this work, we addressed the impact of technology scaling on the performance of phase change memory cells by investigating its effects on both the programming current and the width of the read window. To this end we derived a simplified analytical model of the PCM cell electro-thermal behavior and validate it by means of a 3D finite-elements model of the PCM cell. We considered both constant field and constant voltage scaling approaches. Our study highlights the program-read tradeoffs challenges which aggressive scaling arises and provides analytical insight in the scaling mechanisms.
Acknowledgments
This work has been supported by Italian MIUR in the frame of its National FIRB Project RBAP06L4S5.
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